17ac6a76cSjason-ch chen /* 2*b0208c73SLiju-Clr Chen * Copyright (c) 2022-2023, MediaTek Inc. All rights reserved. 37ac6a76cSjason-ch chen * 47ac6a76cSjason-ch chen * SPDX-License-Identifier: BSD-3-Clause 57ac6a76cSjason-ch chen */ 67ac6a76cSjason-ch chen 77ac6a76cSjason-ch chen #ifndef MT_SPM_CONDIT_H 87ac6a76cSjason-ch chen #define MT_SPM_CONDIT_H 97ac6a76cSjason-ch chen 107ac6a76cSjason-ch chen #include <mt_lp_rm.h> 117ac6a76cSjason-ch chen 127ac6a76cSjason-ch chen enum PLAT_SPM_COND { 137ac6a76cSjason-ch chen PLAT_SPM_COND_MTCMOS1 = 0, 147ac6a76cSjason-ch chen PLAT_SPM_COND_CG_INFRA_0 = 1, 157ac6a76cSjason-ch chen PLAT_SPM_COND_CG_INFRA_1 = 2, 167ac6a76cSjason-ch chen PLAT_SPM_COND_CG_INFRA_2 = 3, 177ac6a76cSjason-ch chen PLAT_SPM_COND_CG_INFRA_3 = 4, 187ac6a76cSjason-ch chen PLAT_SPM_COND_CG_INFRA_4 = 5, 197ac6a76cSjason-ch chen PLAT_SPM_COND_CG_INFRA_5 = 6, 207ac6a76cSjason-ch chen PLAT_SPM_COND_CG_MMSYS_0 = 7, 217ac6a76cSjason-ch chen PLAT_SPM_COND_CG_MMSYS_1 = 8, 227ac6a76cSjason-ch chen PLAT_SPM_COND_CG_MMSYS_2 = 9, 237ac6a76cSjason-ch chen PLAT_SPM_COND_CG_MMSYS_3 = 10, 247ac6a76cSjason-ch chen PLAT_SPM_COND_MAX = 11, 257ac6a76cSjason-ch chen }; 267ac6a76cSjason-ch chen 277ac6a76cSjason-ch chen #define PLL_BIT_UNIVPLL BIT(0) 287ac6a76cSjason-ch chen #define PLL_BIT_MFGPLL BIT(1) 297ac6a76cSjason-ch chen #define PLL_BIT_MSDCPLL BIT(2) 307ac6a76cSjason-ch chen #define PLL_BIT_TVDPLL BIT(3) 317ac6a76cSjason-ch chen #define PLL_BIT_MMPLL BIT(4) 327ac6a76cSjason-ch chen 337ac6a76cSjason-ch chen /* 347ac6a76cSjason-ch chen * Definition about SPM_COND_CHECK_BLOCKED 357ac6a76cSjason-ch chen * bit [00 ~ 15]: cg blocking index 367ac6a76cSjason-ch chen * bit [16 ~ 29]: pll blocking index 377ac6a76cSjason-ch chen * bit [30] : pll blocking information 387ac6a76cSjason-ch chen * bit [31] : idle condition check fail 397ac6a76cSjason-ch chen */ 407ac6a76cSjason-ch chen #define SPM_COND_BLOCKED_CG_IDX U(0) 417ac6a76cSjason-ch chen #define SPM_COND_BLOCKED_PLL_IDX U(16) 427ac6a76cSjason-ch chen #define SPM_COND_CHECK_BLOCKED_PLL BIT(30) 437ac6a76cSjason-ch chen #define SPM_COND_CHECK_FAIL BIT(31) 447ac6a76cSjason-ch chen 457ac6a76cSjason-ch chen struct mt_spm_cond_tables { 467ac6a76cSjason-ch chen char *name; 477ac6a76cSjason-ch chen unsigned int table_cg[PLAT_SPM_COND_MAX]; 487ac6a76cSjason-ch chen unsigned int table_pll; 497ac6a76cSjason-ch chen void *priv; 507ac6a76cSjason-ch chen }; 517ac6a76cSjason-ch chen 527ac6a76cSjason-ch chen extern unsigned int mt_spm_cond_check(int state_id, 537ac6a76cSjason-ch chen const struct mt_spm_cond_tables *src, 547ac6a76cSjason-ch chen const struct mt_spm_cond_tables *dest, 557ac6a76cSjason-ch chen struct mt_spm_cond_tables *res); 567ac6a76cSjason-ch chen 57*b0208c73SLiju-Clr Chen extern int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num, 587ac6a76cSjason-ch chen int stateid, void *priv); 597ac6a76cSjason-ch chen 607ac6a76cSjason-ch chen #endif /* MT_SPM_CONDIT_H */ 61