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Searched refs:r5 (Results 1 – 25 of 25) sorted by relevance

/rk3399_ARM-atf/common/aarch32/
H A Ddebug.S48 ldr r5, =MAX_DEC_DIVISOR
50 udiv r0, r4, r5 /* Get the quotient */
51 mls r4, r0, r5, r4 /* Find the remainder */
54 udiv r5, r5, r6 /* Reduce divisor */
55 cmp r5, #0
76 mov r5, r0
89 mov r4, r5
138 mov r5, #32 /* No of bits to convert to ascii */
144 sub r5, r5, #4
145 lsr r0, r4, r5
[all …]
/rk3399_ARM-atf/plat/allwinner/common/
H A Darisc_off.S60 l.lwz r5, 0x1500(r13) # core output clamps
61 l.or r5, r5, r6 # set bit to ...
62 l.sw 0x1500(r13), r5 # ... activate for our core
64 1: l.lwz r5, 0x1c30(r13) # CPU power-on reset
66 l.and r5, r5, r6 # clear bit to ...
67 l.sw 0x1c30(r13), r5 # ... assert for our core
71 l.slli r6, r6, 2 # r5: core number*4 (0-12)
73 l.ori r5, r0, 0xff # 0xff means all switches off
74 l.sw 0x1540(r6), r5 # core power switch registers
87 l.lwz r5, 0x80(r13) # load C_CPU_STATUS
[all …]
/rk3399_ARM-atf/include/arch/aarch32/
H A Dsmccc_macros.S64 mrs r5, lr_usr
75 mrs r5, lr_svc
95 ldcopr r5, SDCR
96 tst r5, #SDCR_SCCD_BIT
101 ldcopr r5, PMCR
108 str r5, [sp, #SMC_CTX_PMCR]
111 2: orr r5, r5, #PMCR_DP_BIT
112 stcopr r5, PMCR
206 msr lr_usr, r5
217 msr lr_svc, r5
H A Dsmccc_helpers.h44 u_register_t r5; member
138 ((smc_ctx_t *)(_h))->r5 = (_r5); \
H A Darch_helpers.h211 uint32_t r4, uint32_t r5, uint32_t r6, uint32_t r7);
/rk3399_ARM-atf/lib/cpus/aarch32/
H A Dcpu_helpers.S28 ldr r5, =(__CPU_OPS_END__ + CPU_MIDR)
41 cmp r4, r5
99 push {r4 - r5, lr}
101 pop {r4 - r5, pc}
H A Dcortex_a15.S120 mov r5, lr
137 mov lr, r5
H A Dcortex_a17.S110 mov r5, lr
131 mov lr, r5
H A Dcortex_a53.S198 mov r5, lr
225 bx r5
H A Dcortex_a72.S122 mov r5, lr
147 bx r5
H A Dcortex_a57.S440 mov r5, lr
510 bx r5
/rk3399_ARM-atf/plat/rockchip/common/aarch32/
H A Dplat_helpers.S98 and r5, r0, #MPIDR_CPU_MASK
112 add r7, r5, r6, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT
143 ldr r5, =cpuson_entry_point
144 ldr r2, [r5, r7, lsl #2] /* ehem. #3 */
/rk3399_ARM-atf/bl1/aarch32/
H A Dbl1_entrypoint.S74 ldr r5, [r4, #SMC_CTX_SCR]
75 tst r5, #SCR_NS_BIT
H A Dbl1_exceptions.S148 ldr r5, [r4, #SMC_CTX_SCR]
149 tst r5, #SCR_NS_BIT
/rk3399_ARM-atf/drivers/renesas/common/ddr/ddr_a/
H A Dddr_init_v3m.c17 uint32_t i, r2, r5, r6, r7, r12; in init_ddr_v3m_1600() local
195 r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8; in init_ddr_v3m_1600()
221 (((r5 << 1) + r6) & 0xFF)); in init_ddr_v3m_1600()
267 r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8; in init_ddr_v3m_1600()
273 r12 = (r5 >> 2); in init_ddr_v3m_1600()
294 ((r6 + r5 + in init_ddr_v3m_1600()
295 (r5 >> 1) + r12) & 0xFF)); in init_ddr_v3m_1600()
H A Dddr_init_d3.c26 uint32_t i, r2, r3, r5, r6, r7, r12; in init_ddr_d3_1866() local
186 r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; in init_ddr_d3_1866()
212 ((r6 + (r5 << 1)) & 0xFF)); in init_ddr_d3_1866()
259 r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8); in init_ddr_d3_1866()
265 r12 = (r5 >> 0x2); in init_ddr_d3_1866()
287 ((r6 + r5 + in init_ddr_d3_1866()
288 (r5 >> 1) + r12) & 0xFF)); in init_ddr_d3_1866()
361 uint32_t i, r2, r3, r5, r6, r7, r12; in init_ddr_d3_1600() local
533 r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; in init_ddr_d3_1600()
558 ((r6 + (r5 << 1)) & 0xFF)); in init_ddr_d3_1600()
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H A Dddr_init_e3.c37 uint32_t i, r2, r5, r6, r7, r12; in init_ddr() local
378 r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; in init_ddr()
402 ((r6 + ((r5) << 1)) & in init_ddr()
571 r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8); in init_ddr()
576 r12 = (r5 >> 0x2); in init_ddr()
594 mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + r5 + in init_ddr()
595 (r5 >> 1) + r12) & 0xFF)); in init_ddr()
839 uint32_t r2, r5, r6, r7, r12, i; in recovery_from_backup_mode() local
1250 r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; in recovery_from_backup_mode()
1274 r2 | ((r6 + (r5 << 1)) & 0xFF)); in recovery_from_backup_mode()
[all …]
/rk3399_ARM-atf/bl32/sp_min/aarch32/
H A Dentrypoint.S197 ldrd r4, r5, [sp], #8
199 strd r4, r5, [r0, #CPU_DATA_CPU_DATA_PMF_TS]
339 mov r5, r0
357 mov r0, r5
/rk3399_ARM-atf/include/arch/aarch64/
H A Dsmccc_helpers.h139 register uint64_t r5 __asm__("x5") = arg4; in smc_helper()
146 "+r"(r5), "+r"(r6), "+r"(r7)); in smc_helper()
153 ret_args._regs[5] = r5; in smc_helper()
/rk3399_ARM-atf/lib/aarch32/
H A Dcache_helpers.S118 clz r5, r4 // r5 = the bit position of the way size increment
130 orr r0, r1, r9, LSL r5 // factor in the way number and cache level into r0
H A Dmisc_helpers.S30 ldm sp, {r4, r5, r6}
/rk3399_ARM-atf/services/spd/trusty/
H A Dtrusty.c66 uint64_t r5; member
108 args.r5 = 0; in trusty_context_switch()
263 ret.r4, ret.r5, ret.r6, ret.r7); in trusty_smc_handler()
/rk3399_ARM-atf/include/drivers/brcm/emmc/
H A Demmc_csl_sdcmd.h88 struct sd_r5_resp r5; member
/rk3399_ARM-atf/docs/getting_started/
H A Drt-svc-writers-guide.rst276 SMC_RET6(handle, r0, r1, r2, r3, r4, r5);
277 SMC_RET7(handle, r0, r1, r2, r3, r4, r5, r6);
278 SMC_RET8(handle, r0, r1, r2, r3, r4, r5, r6, r7);
/rk3399_ARM-atf/drivers/brcm/emmc/
H A Demmc_csl_sdcard.c887 resp->data.r5.data = rsp0 & 0xff; in process_cmd_response()
894 resp->data.r5.data = rsp0 & 0xff; in process_cmd_response()