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Searched refs:pllxcfgr1 (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32mp2.c741 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; in clk_get_pll_fvco() local
742 uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2; in clk_get_pll_fvco()
743 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3; in clk_get_pll_fvco()
772 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; in _clk_stm32_pll_is_enabled() local
774 return ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_PLLEN) != 0U); in _clk_stm32_pll_is_enabled()
779 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; in _clk_stm32_pll_set_on() local
781 mmio_setbits_32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN); in _clk_stm32_pll_set_on()
786 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; in _clk_stm32_pll_set_off() local
789 mmio_clrbits_32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN); in _clk_stm32_pll_set_off()
795 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; in _clk_stm32_pll_wait_ready_on() local
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H A Dstm32mp1_clk.c500 uint16_t pllxcfgr1; member
572 .pllxcfgr1 = (off2), \
1052 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); in stm32mp1_pll_get_fvco()
1770 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { in stm32mp1_check_pll_conf()
1901 mmio_write_32(rcc_base + pll->pllxcfgr1, value); in stm32mp1_pll_config()