741 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_get_pll_fvco()  local
742 	uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2;  in clk_get_pll_fvco()
743 	uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;  in clk_get_pll_fvco()
772 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in _clk_stm32_pll_is_enabled()  local
774 	return ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_PLLEN) != 0U);  in _clk_stm32_pll_is_enabled()
779 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in _clk_stm32_pll_set_on()  local
781 	mmio_setbits_32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN);  in _clk_stm32_pll_set_on()
786 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in _clk_stm32_pll_set_off()  local
789 	mmio_clrbits_32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN);  in _clk_stm32_pll_set_off()
795 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in _clk_stm32_pll_wait_ready_on()  local
799 	while ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_PLLRDY) == 0U) {  in _clk_stm32_pll_wait_ready_on()
803 			      mmio_read_32(pllxcfgr1));  in _clk_stm32_pll_wait_ready_on()
814 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in _clk_stm32_pll_wait_ready_off()  local
818 	while ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_PLLRDY) != 0U) {  in _clk_stm32_pll_wait_ready_off()
821 			      pll->clk_id - _CK_PLL1 + 1, pllxcfgr1, mmio_read_32(pllxcfgr1));  in _clk_stm32_pll_wait_ready_off()
884 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_recalc_rate()  local
885 	uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;  in clk_stm32_pll_recalc_rate()
886 	uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6;  in clk_stm32_pll_recalc_rate()
887 	uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7;  in clk_stm32_pll_recalc_rate()
1629 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_config_output()  local
1630 	uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2;  in clk_stm32_pll_config_output()
1631 	uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;  in clk_stm32_pll_config_output()
1632 	uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;  in clk_stm32_pll_config_output()
1633 	uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6;  in clk_stm32_pll_config_output()
1634 	uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7;  in clk_stm32_pll_config_output()
1654 		mmio_setbits_32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST);  in clk_stm32_pll_config_output()
1700 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_config_csg()  local
1701 	uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;  in clk_stm32_pll_config_csg()
1702 	uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;  in clk_stm32_pll_config_csg()
1703 	uintptr_t pllxcfgr5 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR5;  in clk_stm32_pll_config_csg()
1720 	mmio_clrbits_32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN);  in clk_stm32_pll_config_csg()
1776 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_wait_mux_ready()  local
1779 	while ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_CKREFST) !=  in clk_stm32_pll_wait_mux_ready()
1794 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in _clk_stm32_pll_init()  local
1823 		mmio_clrbits_32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST);  in _clk_stm32_pll_init()