Searched refs:pllcfg (Results 1 – 3 of 3) sorted by relevance
1736 uint32_t *pllcfg, uint32_t fracv) in stm32mp1_check_pll_conf() argument1762 (pllcfg[PLLCFG_M] + 1U); in stm32mp1_check_pll_conf()1773 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & in stm32mp1_check_pll_conf()1775 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & in stm32mp1_check_pll_conf()1791 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & in stm32mp1_check_pll_conf()1793 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & in stm32mp1_check_pll_conf()1795 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & in stm32mp1_check_pll_conf()1864 uint32_t *pllcfg) in stm32mp1_pll_config_output() argument1870 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & in stm32mp1_pll_config_output()1872 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & in stm32mp1_pll_config_output()[all …]
1892 uint32_t *pllcfg, in clk_stm32_pll_config_output() argument1938 assert(pllcfg[REFDIV] != 0U); in clk_stm32_pll_config_output()1941 (pllcfg[FBDIV] << RCC_PLLxCFGR2_FBDIV_SHIFT) & in clk_stm32_pll_config_output()1944 pllcfg[REFDIV] & RCC_PLLxCFGR2_FREFDIV_MASK); in clk_stm32_pll_config_output()1946 pllcfg[POSTDIV1] & RCC_PLLxCFGR6_POSTDIV1_MASK); in clk_stm32_pll_config_output()1948 pllcfg[POSTDIV2] & RCC_PLLxCFGR7_POSTDIV2_MASK); in clk_stm32_pll_config_output()1950 if ((pllcfg[POSTDIV1] == 0U) || (pllcfg[POSTDIV2] == 0U)) { in clk_stm32_pll_config_output()
8536 …- initialize pllcfg table ([175758b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trust…