1727 				    uint32_t *pllcfg, uint32_t fracv)  in stm32mp1_check_pll_conf()  argument
1753 		 (pllcfg[PLLCFG_M] + 1U);  in stm32mp1_check_pll_conf()
1764 	value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) &  in stm32mp1_check_pll_conf()
1766 	value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) &  in stm32mp1_check_pll_conf()
1782 	value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &  in stm32mp1_check_pll_conf()
1784 	value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) &  in stm32mp1_check_pll_conf()
1786 	value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &  in stm32mp1_check_pll_conf()
1855 				       uint32_t *pllcfg)  in stm32mp1_pll_config_output()  argument
1861 	value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &  in stm32mp1_pll_config_output()
1863 	value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) &  in stm32mp1_pll_config_output()
1865 	value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &  in stm32mp1_pll_config_output()
1871 			       uint32_t *pllcfg, uint32_t fracv)  in stm32mp1_pll_config()  argument
1884 		 (pllcfg[PLLCFG_M] + 1U);  in stm32mp1_pll_config()
1895 	value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) &  in stm32mp1_pll_config()
1897 	value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) &  in stm32mp1_pll_config()
1913 	stm32mp1_pll_config_output(pll_id, pllcfg);  in stm32mp1_pll_config()
1940 				     uint32_t *pllcfg, uint32_t *fracv)  in clk_compute_pll1_settings()  argument
1946 	pllcfg[PLLCFG_Q] = 0U;  in clk_compute_pll1_settings()
1947 	pllcfg[PLLCFG_R] = 0U;  in clk_compute_pll1_settings()
1948 	pllcfg[PLLCFG_O] = PQR(1, 0, 0);  in clk_compute_pll1_settings()
1998 					pllcfg[PLLCFG_M] = divm - 1U;  in clk_compute_pll1_settings()
1999 					pllcfg[PLLCFG_N] = (uint32_t)divn;  in clk_compute_pll1_settings()
2000 					pllcfg[PLLCFG_P] = divp;  in clk_compute_pll1_settings()
2023 				 uint32_t *pllcfg, uint32_t *fracv)  in clk_get_pll1_settings()  argument
2027 	assert(pllcfg != NULL);  in clk_get_pll1_settings()
2045 	return clk_compute_pll1_settings(input_freq, freq_khz, pllcfg, fracv);  in clk_get_pll1_settings()