Searched refs:pll1 (Results 1 – 4 of 4) sorted by relevance
57 pll1: st,pll-1 { label60 pll1_cfg_1200Mhz: pll1-cfg-1200Mhz {
62 pll1: st,pll-1 { label65 pll1_cfg_1200Mhz: pll1-cfg-1200Mhz {
1318 struct stm32_pll_dt_cfg *pll1 = clk_stm32_pll_get_pdata(_PLL1); in clk_compute_pll1_settings() local1342 pll1->output.output[PLL_CFG_Q] = 0U; in clk_compute_pll1_settings()1343 pll1->output.output[PLL_CFG_R] = 0U; in clk_compute_pll1_settings()1393 pll1->vco.src = src; in clk_compute_pll1_settings()1394 pll1->vco.status = RCC_PLLNCR_DIVPEN | RCC_PLLNCR_PLLON; in clk_compute_pll1_settings()1395 pll1->vco.div_mn[PLL_CFG_M] = divm - 1U; in clk_compute_pll1_settings()1396 pll1->vco.div_mn[PLL_CFG_N] = (uint32_t)divn; in clk_compute_pll1_settings()1397 pll1->vco.frac = (uint32_t)frac; in clk_compute_pll1_settings()1398 pll1->output.output[PLL_CFG_P] = divp; in clk_compute_pll1_settings()