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Searched refs:mmio_write_16 (Results 1 – 25 of 28) sorted by relevance

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/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/src/
H A Dddrphy_phyinit_i_loadpieimage.c36 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | C0 | in dfiwrrddatacsconfig_program()
88 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TMASTER | CSR_SEQ0BDLY0_ADDR))), in seq0bdly_program()
91 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TMASTER | CSR_SEQ0BDLY1_ADDR))), in seq0bdly_program()
94 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TMASTER | CSR_SEQ0BDLY2_ADDR))), in seq0bdly_program()
97 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TMASTER | CSR_SEQ0BDLY3_ADDR))), in seq0bdly_program()
111 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG0_ADDR))), in seq0bdisableflag_program()
113 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG1_ADDR))), in seq0bdisableflag_program()
115 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG2_ADDR))), in seq0bdisableflag_program()
117 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG3_ADDR))), in seq0bdisableflag_program()
119 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG4_ADDR))), in seq0bdisableflag_program()
[all …]
H A Dddrphy_phyinit_writeoutmem.c37 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), in ddrphy_phyinit_writeoutmem()
43 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * ((index * 2) + mem_offset))), in ddrphy_phyinit_writeoutmem()
45 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * ((index * 2) + 1 + mem_offset))), in ddrphy_phyinit_writeoutmem()
53 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), in ddrphy_phyinit_writeoutmem()
66 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), in ddrphy_phyinit_writeoutmsgblk()
70 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (index + mem_offset))), mem[index]); in ddrphy_phyinit_writeoutmsgblk()
77 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), in ddrphy_phyinit_writeoutmsgblk()
H A Dddrphy_phyinit_restore_sequence.c44 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), in ddrphy_phyinit_restore_sequence()
51 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))), in ddrphy_phyinit_restore_sequence()
58 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_CALZAP_ADDR))), 0x1U); in ddrphy_phyinit_restore_sequence()
70 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))), in ddrphy_phyinit_restore_sequence()
74 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), in ddrphy_phyinit_restore_sequence()
H A Dddrphy_phyinit_g_execfw.c42 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), in ddrphy_phyinit_g_execfw()
44 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICRORESET_ADDR))), in ddrphy_phyinit_g_execfw()
46 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICRORESET_ADDR))), in ddrphy_phyinit_g_execfw()
50 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICRORESET_ADDR))), 0x0U); in ddrphy_phyinit_g_execfw()
62 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICRORESET_ADDR))), in ddrphy_phyinit_g_execfw()
H A Dddrphy_phyinit_c_initphyconfig.c56 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDBYTE | c_addr | b_addr | in txslewrate_program()
115 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TANIB | c_addr | in atxslewrate_program()
132 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | in dfidatacsdestmap_program()
135 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | in dfidatacsdestmap_program()
167 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_PLLCTRL2_ADDR))), pllctrl2); in pllctrl2_program()
202 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_ARDPTRINITVAL_ADDR))), in ardptrinitval_program()
215 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | C0 | CSR_SEQ0BGPR4_ADDR))), 0U); in procodtctl_program()
296 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DQSPREAMBLECONTROL_ADDR))), in dbytedllmodecntrl_program()
300 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DBYTEDLLMODECNTRL_ADDR))), in dbytedllmodecntrl_program()
307 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DLLLOCKPARAM_ADDR))), in dbytedllmodecntrl_program()
[all …]
H A Dddrphy_phyinit_progcsrskiptrain.c76 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDBYTE | c_addr | in dfimrl_program()
81 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_HWTMRL_ADDR))), dfimrl); in dfimrl_program()
158 mmio_write_16((uintptr_t)
167 mmio_write_16((uintptr_t)
237 mmio_write_16((uintptr_t)
246 mmio_write_16((uintptr_t)
338 mmio_write_16((uintptr_t)
347 mmio_write_16((uintptr_t)
491 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (P0 | C0 | TINITENG | R2 |
496 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (P0 | C0 | TINITENG | R2 |
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H A Dddrphy_phyinit_d_loadimem.c39 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_MEMRESETL_ADDR))), memresetl); in ddrphy_phyinit_d_loadimem()
H A Dddrphy_phyinit_loadpieprodcode.c186 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * prodcode_addr[i])), in ddrphy_phyinit_loadpieprodcode()
H A Dddrphy_phyinit_reginterface.c153 mmio_write_16((uintptr_t) in ddrphy_phyinit_reginterface()
/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/usercustom/
H A Dddrphy_phyinit_usercustom_custompretrain.c56 mmio_write_16(base + (i * sizeof(uint32_t)), in ddrphy_phyinit_usercustom_custompretrain()
71 mmio_write_16(base + (j * sizeof(uint32_t)), in ddrphy_phyinit_usercustom_custompretrain()
79 mmio_write_16(base + (j * sizeof(uint32_t)), in ddrphy_phyinit_usercustom_custompretrain()
86 mmio_write_16(base + (j * sizeof(uint32_t)), in ddrphy_phyinit_usercustom_custompretrain()
H A Dddrphy_phyinit_usercustom_g_waitfwdone.c51 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_DCTWRITEPROT_ADDR))), 0U); in ack_message_receipt()
61 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_DCTWRITEPROT_ADDR))), 1U); in ack_message_receipt()
H A Dddrphy_phyinit_usercustom_saveretregs.c366 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), in ddrphy_phyinit_usercustom_saveretregs()
368 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))), in ddrphy_phyinit_usercustom_saveretregs()
392 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))), in ddrphy_phyinit_usercustom_saveretregs()
395 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), in ddrphy_phyinit_usercustom_saveretregs()
/rk3399_ARM-atf/drivers/renesas/common/dma/
H A Ddma_driver.c84 mmio_write_16(DMA_DMAOR, 0); in dma_setup()
90 mmio_write_16(DMA_DMAOR, DMAOR_INITIAL); in dma_start()
115 mmio_write_16(DMA_DMAOR, 0); in dma_end()
/rk3399_ARM-atf/include/lib/
H A Dmmio.h22 static inline void mmio_write_16(uintptr_t addr, uint16_t value) in mmio_write_16() function
36 mmio_write_16(addr, (mmio_read_16(addr) & ~clear) | set); in mmio_clrsetbits_16()
/rk3399_ARM-atf/plat/imx/imx8m/
H A Dimx8m_psci_common.c202 mmio_write_16(wdog_base, val); in imx_wdog_restart()
204 mmio_write_16(wdog_base + WDOG_WSR, 0x5555); in imx_wdog_restart()
205 mmio_write_16(wdog_base + WDOG_WSR, 0xaaaa); in imx_wdog_restart()
/rk3399_ARM-atf/plat/imx/common/
H A Dimx_wdog.c16 mmio_write_16((uintptr_t)&wdog->wmcr, 0); in imx_wdog_power_down()
/rk3399_ARM-atf/plat/socionext/uniphier/
H A Duniphier_emmc.c113 mmio_write_16(host_base + SDHCI_TRANSFER_MODE, mode); in uniphier_emmc_send_cmd()
136 mmio_write_16(host_base + SDHCI_COMMAND, in uniphier_emmc_send_cmd()
200 mmio_write_16(host_base + SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(7, 512)); in uniphier_emmc_load_image()
201 mmio_write_16(host_base + SDHCI_BLOCK_COUNT, block_cnt); in uniphier_emmc_load_image()
/rk3399_ARM-atf/plat/brcm/board/stingray/include/
H A Dscp_utils.h27 #define SCP_WRITE_CFG16(cfg, value) mmio_write_16(CRMU_CFG_BASE + \
/rk3399_ARM-atf/drivers/marvell/
H A Dddr_phy_access.c31 mmio_write_16(DDR_PHY_BASE_ADDR + (2 * offset), data); in snps_fw_write()
/rk3399_ARM-atf/drivers/renesas/common/scif/
H A Dscif-common.c25 mmio_write_16(addr, mmio_read_16(addr) & ~clear); in scif_clrbits_16()
/rk3399_ARM-atf/plat/rpi/common/
H A Drpi_pci_svc.c176 mmio_write_16(base, val); in pci_write_config()
/rk3399_ARM-atf/drivers/cadence/emmc/
H A Dcdns_sdmmc.c613 mmio_write_16(cdns_params.reg_base + SDHC_CDNS_SRS03, mode); in cdns_send_cmd()
620 mmio_write_16((cdns_params.reg_base + CICE_OFFSET), in cdns_send_cmd()
/rk3399_ARM-atf/drivers/st/fmc/
H A Dstm32_fmc2_nand.c632 mmio_write_16(data_base, *(uint16_t *)buff); in stm32_fmc2_write_data()
646 mmio_write_16(data_base, *(uint16_t *)buff); in stm32_fmc2_write_data()
/rk3399_ARM-atf/drivers/renesas/rcar/pfc/M3/
H A Dpfc_init_m3.c628 mmio_write_16(RTDMAC_RDMOR, RDMOR_DME); in start_rtdma0_descriptor()
661 mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */ in pfc_reg_write()
665 mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */ in pfc_reg_write()
/rk3399_ARM-atf/drivers/renesas/rzg/pfc/G2M/
H A Dpfc_init_g2m.c628 mmio_write_16(RTDMAC_RDMOR, RDMOR_DME); in start_rtdma0_descriptor()
661 mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */ in pfc_reg_write()
665 mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */ in pfc_reg_write()

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