1 /*
2 * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8
9 #include <ddrphy_phyinit.h>
10
11 #include <lib/mmio.h>
12
13 #include <platform_def.h>
14
15 /*
16 * This function implements the register restore portion of S3/IO
17 * retention sequence.
18 *
19 * \note This function requiers the runtime_config.reten=1 to enable PhyInit exit retention feature.
20 * This variable can be set as in
21 * \return 0 on completion of the sequence, EXIT_FAILURE on error.
22 */
ddrphy_phyinit_restore_sequence(void)23 int ddrphy_phyinit_restore_sequence(void)
24 {
25 int ret;
26
27 /*
28 * Before you call this functions perform the following:
29 * --------------------------------------------------------------------------
30 * -# Bring up VDD, VDDQ should already be up
31 * -# Since the CKE* and MEMRESET pin state must be protected, special care
32 * must be taken to ensure that the following signals
33 * - atpg_mode = 1'b0
34 * - PwrOkIn = 1'b0
35 *
36 * -# The {BypassModeEn*, WRSTN} signals may be defined at VDD power-on, but
37 * must be driven to ZERO at least 10ns prior to the asserting edge of PwrOkIn.
38 *
39 * -# Start Clocks and Reset the PHY
40 * This step is identical to ddrphy_phyinit_usercustom_b_startclockresetphy()
41 */
42
43 /* Write the MicroContMuxSel CSR to 0x0 to allow access to the internal CSRs */
44 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))),
45 0x0U);
46
47 /*
48 * Write the UcclkHclkEnables CSR to 0x3 to enable all the clocks so the reads can
49 * complete.
50 */
51 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))),
52 0x3U);
53
54 /*
55 * Assert CalZap to force impedance calibration FSM to idle.
56 * De-asserted as part of dfi_init_start/complete handshake by the PIE when DfiClk is valid.
57 */
58 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_CALZAP_ADDR))), 0x1U);
59
60 /* Issue register writes to restore registers values */
61 ret = ddrphy_phyinit_reginterface(RESTOREREGS, 0U, 0U);
62 if (ret != 0) {
63 return ret;
64 }
65
66 /*
67 * Write the UcclkHclkEnables CSR to disable the appropriate clocks after all reads done.
68 * Disabling Ucclk (PMU) and Hclk (training hardware).
69 */
70 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))),
71 0x0U);
72
73 /* Write the MicroContMuxSel CSR to 0x1 to isolate the internal CSRs during mission mode */
74 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))),
75 0x1U);
76
77 return 0;
78 }
79