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/rk3399_ARM-atf/plat/nxp/common/soc_errata/
H A Derrata_a050426.c13 uint32_t i, val3, val4; in erratum_a050426() local
31 for (i = 0U; i < 4U; i++) { in erratum_a050426()
32 mmio_write_32(0x706312000 + (i * 4), 0x55555555); in erratum_a050426()
33 mmio_write_32(0x706312400 + (i * 4), 0x55555555); in erratum_a050426()
34 mmio_write_32(0x706312800 + (i * 4), 0x55555555); in erratum_a050426()
35 mmio_write_32(0x706314000 + (i * 4), 0x55555555); in erratum_a050426()
36 mmio_write_32(0x706314400 + (i * 4), 0x55555555); in erratum_a050426()
37 mmio_write_32(0x706314800 + (i * 4), 0x55555555); in erratum_a050426()
38 mmio_write_32(0x706314c00 + (i * 4), 0x55555555); in erratum_a050426()
40 for (i = 0U; i < 3U; i++) { in erratum_a050426()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/soc/
H A Dsoc.h32 #define CRU_PLLS_CON(pll_id, i) ((pll_id) * 0x20 + (i) * 0x4) argument
33 #define CRU_PLL_CON(i) ((i) * 0x4) argument
35 #define CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300) argument
37 #define CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) argument
39 #define CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00) argument
65 #define LCORE_CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300) argument
67 #define LCORE_CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) argument
69 #define LCORE_CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00) argument
74 #define BCORE_CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300) argument
76 #define BCORE_CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) argument
[all …]
/rk3399_ARM-atf/plat/imx/imx8ulp/
H A Dapd_context.c21 #define S400_MU_TRx(i) (S400_MU_BASE + 0x200 + (i) * 4) argument
22 #define S400_MU_RRx(i) (S400_MU_BASE + 0x280 + (i) * 4) argument
148 unsigned int i, j; in apd_io_pad_off() local
151 for (i = 0; i < PORTS_NUM; i++) { in apd_io_pad_off()
152 for (j = 0; j < iomuxc_sections[i].reg_num; j++) { in apd_io_pad_off()
153 mmio_write_32(iomuxc_sections[i].offset + j * 4, 0); in apd_io_pad_off()
163 unsigned int i, j; in iomuxc_save() local
166 for (i = 0U; i < IOMUXC_SECTION_NUM; i++) { in iomuxc_save()
167 for (j = 0U; j < iomuxc_sections[i].reg_num; j++) { in iomuxc_save()
168 iomuxc_ctx[index++] = mmio_read_32(iomuxc_sections[i].offset + j * 4); in iomuxc_save()
[all …]
/rk3399_ARM-atf/plat/imx/imx9/common/
H A Dimx9_sys_sleep.c54 for (uint32_t i = 0U; i < GPIO_CTRL_REG_NUM; i++) { in gpio_save() local
56 if (i < 4U) { in gpio_save()
57 ctx->port_ctrl[i] = mmio_read_32(ctx->base + gpio_ctrl_offset[i]); in gpio_save()
59 mmio_write_32(ctx->base + gpio_ctrl_offset[i], 0x0); in gpio_save()
61 ctx->port_ctrl[i] = mmio_read_32(ctx->base + gpio_ctrl_offset[i]); in gpio_save()
66 for (uint32_t i = 0U; i < ctx->pin_num; i++) { in gpio_save() local
67 ctx->gpio_icr[i] = mmio_read_32(ctx->base + 0x80 + i * 4U); in gpio_save()
69 if (ctx->gpio_icr[i]) { in gpio_save()
75 for (uint32_t i = 0U; i < 4U; i++) { in gpio_save() local
76 mmio_write_32(ctx->base + gpio_ctrl_offset[i], ctx->port_ctrl[i]); in gpio_save()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/apusys/devapc/
H A Dapusys_dapc_v1.c20 uint32_t i; in set_apusys_dapc_v1() local
26 for (i = 0; i < size; i++) { in set_apusys_dapc_v1()
27 ret += cfg(i, DOMAIN_0, dapc[i].d0_permission); in set_apusys_dapc_v1()
28 ret += cfg(i, DOMAIN_1, dapc[i].d1_permission); in set_apusys_dapc_v1()
29 ret += cfg(i, DOMAIN_2, dapc[i].d2_permission); in set_apusys_dapc_v1()
30 ret += cfg(i, DOMAIN_3, dapc[i].d3_permission); in set_apusys_dapc_v1()
31 ret += cfg(i, DOMAIN_4, dapc[i].d4_permission); in set_apusys_dapc_v1()
32 ret += cfg(i, DOMAIN_5, dapc[i].d5_permission); in set_apusys_dapc_v1()
33 ret += cfg(i, DOMAIN_6, dapc[i].d6_permission); in set_apusys_dapc_v1()
34 ret += cfg(i, DOMAIN_7, dapc[i].d7_permission); in set_apusys_dapc_v1()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/secure/
H A Dsecure.h11 #define DSU_SGRF_SOC_CON(i) ((i) * 4) argument
12 #define DSUSGRF_SOC_CON(i) ((i) * 4) argument
14 #define DSUSGRF_DDR_HASH_CON(i) (0x240 + (i) * 4) argument
21 #define SGRF_SOC_CON(i) ((i) * 4) argument
22 #define SGRF_FIREWALL_CON(i) (0x240 + (i) * 4) argument
26 #define FIREWALL_DDR_RGN(i) ((i) * 0x4) argument
28 #define FIREWALL_DDR_MST(i) (0x40 + (i) * 0x4) argument
32 #define FIREWALL_SYSMEM_RGN(i) ((i) * 0x4) argument
34 #define FIREWALL_SYSMEM_MST(i) (0x40 + (i) * 0x4) argument
38 #define FIREWALL_DSU_RGN(i) ((i) * 0x4) argument
[all …]
H A Dsecure.c17 uint32_t i; in secure_fw_master_init() local
29 for (i = 0; i < FIREWALL_DDR_MST_CNT; i++) { in secure_fw_master_init()
30 if (i == 1 || i == 14 || i == 36) in secure_fw_master_init()
33 mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_MST(i), 0xffffffff); in secure_fw_master_init()
44 for (i = 0; i < FIREWALL_SYSMEM_MST_CNT; i++) { in secure_fw_master_init()
45 if (i == 19 || i == 38 || i == 41) in secure_fw_master_init()
48 mmio_write_32(FIREWALL_SYSMEM_BASE + FIREWALL_SYSMEM_MST(i), in secure_fw_master_init()
62 int i; in dsu_fw_rgn_config() local
72 for (i = 0; i < DDR_CHN_CNT; i++) in dsu_fw_rgn_config()
73 mmio_setbits_32(FIREWALL_DSU_BASE + FIREWALL_DSU_CON(i), in dsu_fw_rgn_config()
[all …]
/rk3399_ARM-atf/drivers/nxp/flexspi/nor/
H A Dtest_fspi.c31 uint32_t failed, i; in fspi_test() local
43 for (i = 0; i < size; i++) in fspi_test()
44 if (fspi_swap32(0xffffffff) != buffer[i]) { in fspi_test()
50 NOTICE("[%d]: Success Erase: data in buffer[%d] 0x%08x\n", __LINE__, i-3, buffer[i-3]); in fspi_test()
52 ERROR("Erase: Failed -->xxx with buffer[%d]=0x%08x\n", i, buffer[i]); in fspi_test()
55 for (i = 0; i < SIZE_BUFFER; i++) in fspi_test()
56 buffer[i] = 0x12345678; in fspi_test()
63 for (i = 0; i < size; i++) in fspi_test()
64 if (fspi_swap32(0x12345678) != buffer[i]) { in fspi_test()
70 NOTICE("[%d]: Success IpWrite with IP READ in buffer[%d] 0x%08x\n", __LINE__, i-3, buffer[i-3]); in fspi_test()
[all …]
/rk3399_ARM-atf/plat/nxp/common/setup/
H A Dls_common.c63 int i = 0; in mmap_add_ddr_regions_statically() local
66 VERBOSE("DRAM Region %d: %p - %p\n", i, in mmap_add_ddr_regions_statically()
67 (void *) info_dram_regions->region[i].addr, in mmap_add_ddr_regions_statically()
68 (void *) (info_dram_regions->region[i].addr in mmap_add_ddr_regions_statically()
69 + info_dram_regions->region[i].size in mmap_add_ddr_regions_statically()
71 mmap_add_region(info_dram_regions->region[i].addr, in mmap_add_ddr_regions_statically()
72 info_dram_regions->region[i].addr, in mmap_add_ddr_regions_statically()
73 info_dram_regions->region[i].size, in mmap_add_ddr_regions_statically()
77 if (info_dram_regions->region[i].size > in mmap_add_ddr_regions_statically()
79 VERBOSE("Secure DRAM Region %d: %p - %p\n", i, in mmap_add_ddr_regions_statically()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/secure/
H A Dfirewall.c408 int i; in fw_buf_add_msts() local
410 for (i = 0; FW_GET_TYPE(mst_ids[i]) != FW_INVLID_SLV_ID; i++) in fw_buf_add_msts()
411 fw_buf_mst_dm_cfg(mst_ids[i], dm_id); in fw_buf_add_msts()
416 int i; in fw_buf_add_slvs() local
418 for (i = 0; FW_GET_TYPE(slv_ids[i]) != FW_INVLID_SLV_ID; i++) in fw_buf_add_slvs()
419 fw_buf_slv_grp_cfg(slv_ids[i], grp_id); in fw_buf_add_slvs()
445 int i; in fw_domain_init() local
448 for (i = 0; i < FW_SGRF_MST_DOMAIN_CON_CNT; i++) in fw_domain_init()
449 fw_config_buf.domain[i] = 0x0; in fw_domain_init()
457 int i; in fw_slv_grp_init() local
[all …]
H A Dsecure.h12 #define PMU0SGRF_SOC_CON(i) ((i) * 4) argument
15 #define PMU1SGRF_SOC_CON(i) ((i) * 4) argument
18 #define CCISGRF_SOC_CON(i) (0x20 + (i) * 4) argument
19 #define CCISGRF_DDR_HASH_CON(i) (0x40 + (i) * 4) argument
22 #define SYSSGRF_DDR_BANK_MSK(i) (0x04 + (i) * 4) argument
23 #define SYSSGRF_DDR_CH_MSK(i) (0x18 + (i) * 4) argument
24 #define SYSSGRF_SOC_CON(i) (0x20 + (i) * 4) argument
25 #define SYSSGRF_DMAC_CON(i) (0x80 + (i) * 4) argument
/rk3399_ARM-atf/plat/intel/soc/stratix10/soc/
H A Ds10_pinmux.c190 unsigned int i; in config_pinmux() local
192 for (i = 0; i < 96; i += 2) { in config_pinmux()
194 hoff_ptr->pinmux_sel_array[i], in config_pinmux()
195 hoff_ptr->pinmux_sel_array[i+1]); in config_pinmux()
198 for (i = 0; i < 96; i += 2) { in config_pinmux()
200 hoff_ptr->pinmux_io_array[i], in config_pinmux()
201 hoff_ptr->pinmux_io_array[i+1]); in config_pinmux()
204 for (i = 0; i < 42; i += 2) { in config_pinmux()
206 hoff_ptr->pinmux_fpga_array[i], in config_pinmux()
207 hoff_ptr->pinmux_fpga_array[i+1]); in config_pinmux()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/
H A Dpmu.h19 #define PMU0_DDR_RET_CON(i) (0x0020 + (i) * 4) argument
30 #define PMU1_DDR_PWR_CON(i) (0x4020 + (i) * 4) argument
31 #define PMU1_DDR_PWR_SFTCON(i) (0x4030 + (i) * 4) argument
37 #define PMU1_PLLPD_CON(i) (0x4060 + (i) * 4) argument
38 #define PMU1_PLLPD_SFTCON(i) (0x4068 + (i) * 4) argument
45 #define PMU1_SYS_REG(i) (0x4100 + (i) * 4) argument
51 #define PMU2_CPU_AUTO_PWR_CON(i) (0x8010 + (i) * 4) argument
52 #define PMU2_CPU_PWR_SFTCON(i) (0x8030 + (i) * 4) argument
53 #define PMU2_CORE_PWR_CON(i) (0x8050 + (i) * 4) argument
54 #define PMU2_CORE_PWR_SFTCON(i) (0x8058 + (i) * 4) argument
[all …]
/rk3399_ARM-atf/plat/arm/common/fconf/
H A Dfconf_sdei_getter.c13 #define PRIVATE_EVENT_NUM(i) private_events[3 * (i)] argument
14 #define PRIVATE_EVENT_INTR(i) private_events[3 * (i) + 1] argument
15 #define PRIVATE_EVENT_FLAGS(i) private_events[3 * (i) + 2] argument
17 #define SHARED_EVENT_NUM(i) shared_events[3 * (i)] argument
18 #define SHARED_EVENT_INTR(i) shared_events[3 * (i) + 1] argument
19 #define SHARED_EVENT_FLAGS(i) shared_events[3 * (i) + 2] argument
25 uint32_t i; in fconf_populate_sdei_dyn_config() local
64 for (i = 0; i < sdei_dyn_config.private_ev_cnt; i++) { in fconf_populate_sdei_dyn_config()
65 sdei_dyn_config.private_ev_nums[i] = PRIVATE_EVENT_NUM(i); in fconf_populate_sdei_dyn_config()
66 sdei_dyn_config.private_ev_intrs[i] = PRIVATE_EVENT_INTR(i); in fconf_populate_sdei_dyn_config()
[all …]
H A Dfconf_sec_intr_config.c13 #define G0_INTR_NUM(i) g0_intr_prop[3U * (i)] argument
14 #define G0_INTR_PRIORITY(i) g0_intr_prop[3U * (i) + 1] argument
15 #define G0_INTR_CONFIG(i) g0_intr_prop[3U * (i) + 2] argument
17 #define G1S_INTR_NUM(i) g1s_intr_prop[3U * (i)] argument
18 #define G1S_INTR_PRIORITY(i) g1s_intr_prop[3U * (i) + 1] argument
19 #define G1S_INTR_CONFIG(i) g1s_intr_prop[3U * (i) + 2] argument
103 for (uint32_t i = 0; i < g0_intr_count; i++) { in fconf_populate_sec_intr_config() local
108 sec_intr_property.intr_num = G0_INTR_NUM(i); in fconf_populate_sec_intr_config()
109 sec_intr_property.intr_pri = G0_INTR_PRIORITY(i); in fconf_populate_sec_intr_config()
110 sec_intr_property.intr_cfg = G0_INTR_CONFIG(i); in fconf_populate_sec_intr_config()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/pmu/
H A Dpmu.h25 #define PMU0_DDR_RET_CON(i) (0x0020 + (i) * 4) argument
34 #define PMU1_DDR_PWR_CON(i) (PMU1_OFFSET + 0x0100 + (i) * 4) argument
35 #define PMU1_DDR_PWR_SFTCON(i) (PMU1_OFFSET + 0x0110 + (i) * 4) argument
36 #define PMU1_DDR_AXIPWR_CON(i) (PMU1_OFFSET + 0x0120 + (i) * 4) argument
37 #define PMU1_DDR_AXIPWR_SFTCON(i) (PMU1_OFFSET + 0x0130 + (i) * 4) argument
41 #define PMU1_CRU_PWR_CON(i) (PMU1_OFFSET + 0x0200 + (i) * 4) argument
42 #define PMU1_CRU_PWR_SFTCON(i) (PMU1_OFFSET + 0x0208 + (i) * 4) argument
44 #define PMU1_PLLPD_CON(i) (PMU1_OFFSET + 0x0220 + (i) * 4) argument
45 #define PMU1_PLLPD_SFTCON(i) (PMU1_OFFSET + 0x0228 + (i) * 4) argument
62 #define PMU2_DBG_PWR_CON(i) (PMU2_OFFSET + 0x001c + (i) * 4) argument
[all …]
/rk3399_ARM-atf/plat/rockchip/px30/drivers/soc/
H A Dsoc.c48 uint32_t i, j; in clk_gate_con_save() local
50 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) in clk_gate_con_save()
51 clkgt_save[i] = in clk_gate_con_save()
52 mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(i)); in clk_gate_con_save()
53 j = i; in clk_gate_con_save()
54 for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++, j++) in clk_gate_con_save()
56 mmio_read_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i)); in clk_gate_con_save()
61 uint32_t i, j; in clk_gate_con_restore() local
63 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) in clk_gate_con_restore()
64 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), in clk_gate_con_restore()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/
H A Ddfs.c184 uint32_t i, j; in sdram_timing_cfg_init() local
186 for (i = 0; i < sdram_params->num_channels; i++) { in sdram_timing_cfg_init()
187 ptiming_config->dram_info[i].speed_rate = DDR3_DEFAULT; in sdram_timing_cfg_init()
188 ptiming_config->dram_info[i].cs_cnt = sdram_params->ch[i].rank; in sdram_timing_cfg_init()
189 for (j = 0; j < sdram_params->ch[i].rank; j++) { in sdram_timing_cfg_init()
190 ptiming_config->dram_info[i].per_die_capability[j] = in sdram_timing_cfg_init()
191 get_cs_die_capability(sdram_params, i, j); in sdram_timing_cfg_init()
264 uint32_t i; in get_rdlat_adj() local
277 for (i = 0; i < cnt; i++) { in get_rdlat_adj()
278 if (cl == p[i].cl) in get_rdlat_adj()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm_cond.c24 unsigned int i = 0; in mt_spm_cond_check() local
30 for (i = 0; i < cond_info->idle_cond_num; i++) { in mt_spm_cond_check()
32 res->table_cg[i] = in mt_spm_cond_check()
33 (src->table_cg[i] & dest->table_cg[i]); in mt_spm_cond_check()
35 if (res->table_cg[i]) in mt_spm_cond_check()
36 b_res |= (((uint64_t)1) << i); in mt_spm_cond_check()
38 } else if (src->table_cg[i] & dest->table_cg[i]) { in mt_spm_cond_check()
39 b_res |= (((uint64_t)1) << i); in mt_spm_cond_check()
77 int i, res; in mt_spm_cond_update() local
91 for (i = 0; i < cond_info->idle_cond_num; i++) { in mt_spm_cond_update()
[all …]
/rk3399_ARM-atf/drivers/arm/rse/
H A Drse_comms_protocol_embed.c25 uint32_t i; in rse_protocol_embed_serialize_msg() local
35 for (i = 0U; i < in_len; ++i) { in rse_protocol_embed_serialize_msg()
36 msg->io_size[i] = in_vec[i].len; in rse_protocol_embed_serialize_msg()
38 for (i = 0U; i < out_len; ++i) { in rse_protocol_embed_serialize_msg()
39 msg->io_size[in_len + i] = out_vec[i].len; in rse_protocol_embed_serialize_msg()
42 for (i = 0U; i < in_len; ++i) { in rse_protocol_embed_serialize_msg()
43 if (in_vec[i].len > sizeof(msg->trailer) - payload_size) { in rse_protocol_embed_serialize_msg()
47 in_vec[i].base, in rse_protocol_embed_serialize_msg()
48 in_vec[i].len); in rse_protocol_embed_serialize_msg()
49 payload_size += in_vec[i].len; in rse_protocol_embed_serialize_msg()
[all …]
H A Drse_comms_protocol_pointer_access.c21 unsigned int i; in rse_protocol_pointer_access_serialize_msg() local
31 for (i = 0U; i < in_len; ++i) { in rse_protocol_pointer_access_serialize_msg()
32 msg->io_sizes[i] = in_vec[i].len; in rse_protocol_pointer_access_serialize_msg()
33 msg->host_ptrs[i] = (uint64_t)in_vec[i].base; in rse_protocol_pointer_access_serialize_msg()
35 for (i = 0U; i < out_len; ++i) { in rse_protocol_pointer_access_serialize_msg()
36 msg->io_sizes[in_len + i] = out_vec[i].len; in rse_protocol_pointer_access_serialize_msg()
37 msg->host_ptrs[in_len + i] = (uint64_t)out_vec[i].base; in rse_protocol_pointer_access_serialize_msg()
51 unsigned int i; in rse_protocol_pointer_access_deserialize_reply() local
56 for (i = 0U; i < out_len; ++i) { in rse_protocol_pointer_access_deserialize_reply()
57 out_vec[i].len = reply->out_sizes[i]; in rse_protocol_pointer_access_deserialize_reply()
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_pinmux.c217 unsigned int i; in config_pinmux() local
219 for (i = 0; i < 96; i += 2) { in config_pinmux()
221 hoff_ptr->pinmux_sel_array[i], in config_pinmux()
222 hoff_ptr->pinmux_sel_array[i+1]); in config_pinmux()
225 for (i = 0; i < 96; i += 2) { in config_pinmux()
227 hoff_ptr->pinmux_io_array[i], in config_pinmux()
228 hoff_ptr->pinmux_io_array[i+1]); in config_pinmux()
231 for (i = 0; i < 40; i += 2) { in config_pinmux()
233 hoff_ptr->pinmux_fpga_array[i], in config_pinmux()
234 hoff_ptr->pinmux_fpga_array[i+1]); in config_pinmux()
[all …]
/rk3399_ARM-atf/drivers/arm/gic/v3/
H A Dgicv3_helpers.c164 unsigned int i, num_ints; in gicv3_spis_config_defaults() local
173 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IGROUPR_SHIFT)) { in gicv3_spis_config_defaults()
174 gicd_write_igroupr(gicv3_get_multichip_base(i, gicd_base), i, ~0U); in gicv3_spis_config_defaults()
182 for (i = MIN_ESPI_ID; i < num_eints; in gicv3_spis_config_defaults()
183 i += (1U << IGROUPR_SHIFT)) { in gicv3_spis_config_defaults()
184 gicd_write_igroupr(gicv3_get_multichip_base(i, gicd_base), i, ~0U); in gicv3_spis_config_defaults()
192 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IPRIORITYR_SHIFT)) { in gicv3_spis_config_defaults()
193 gicd_write_ipriorityr(gicv3_get_multichip_base(i, gicd_base), i, GICD_IPRIORITYR_DEF_VAL); in gicv3_spis_config_defaults()
197 for (i = MIN_ESPI_ID; i < num_eints; in gicv3_spis_config_defaults()
198 i += (1U << IPRIORITYR_SHIFT)) { in gicv3_spis_config_defaults()
[all …]
/rk3399_ARM-atf/tools/cert_create/src/
H A Dmain.c93 int rem, i = 0; in print_help() local
124 printf("\t%-32s %s\n", line, cmd_opt_get_help_msg(i)); in print_help()
126 i++; in print_help()
133 int i; in get_key_alg() local
135 for (i = 0 ; i < NUM_ELEM(key_algs_str) ; i++) { in get_key_alg()
136 if (0 == strcmp(key_alg_str, key_algs_str[i])) { in get_key_alg()
137 return i; in get_key_alg()
158 int i; in get_hash_alg() local
160 for (i = 0 ; i < NUM_ELEM(hash_algs_str) ; i++) { in get_hash_alg()
161 if (0 == strcmp(hash_alg_str, hash_algs_str[i])) { in get_hash_alg()
[all …]
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_pinmux.c225 uint32_t i; in config_pinmux() local
228 for (i = 0; i < ARRAY_SIZE(hoff_ptr->pinmux_sel_array); i += 2) { in config_pinmux()
229 mmio_write_32(AGX5_PINMUX_PIN0SEL + hoff_ptr->pinmux_sel_array[i], in config_pinmux()
230 hoff_ptr->pinmux_sel_array[i+1]); in config_pinmux()
234 for (i = 0; i < ARRAY_SIZE(hoff_ptr->pinmux_io_array); i += 2) { in config_pinmux()
235 mmio_write_32(AGX5_PINMUX_IO0CTRL + hoff_ptr->pinmux_io_array[i], in config_pinmux()
236 hoff_ptr->pinmux_io_array[i+1]); in config_pinmux()
245 for (i = 0; i < (ARRAY_SIZE(hoff_ptr->pinmux_fpga_array) - 4); i += 2) { in config_pinmux()
246 mmio_write_32(AGX5_PINMUX_EMAC0_USEFPGA + hoff_ptr->pinmux_fpga_array[i], in config_pinmux()
247 hoff_ptr->pinmux_fpga_array[i+1]); in config_pinmux()
[all …]

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