54 	for (uint32_t i = 0U; i < GPIO_CTRL_REG_NUM; i++) {  in gpio_save()  local
56 		if (i < 4U) {  in gpio_save()
57 			ctx->port_ctrl[i] = mmio_read_32(ctx->base + gpio_ctrl_offset[i]);  in gpio_save()
59 			mmio_write_32(ctx->base + gpio_ctrl_offset[i], 0x0);  in gpio_save()
61 			ctx->port_ctrl[i] = mmio_read_32(ctx->base + gpio_ctrl_offset[i]);  in gpio_save()
66 	for (uint32_t i = 0U; i < ctx->pin_num; i++) {  in gpio_save()  local
67 		ctx->gpio_icr[i] = mmio_read_32(ctx->base + 0x80 + i * 4U);  in gpio_save()
69 		if (ctx->gpio_icr[i]) {  in gpio_save()
75 	for (uint32_t i = 0U; i < 4U; i++) {  in gpio_save()  local
76 		mmio_write_32(ctx->base + gpio_ctrl_offset[i], ctx->port_ctrl[i]);  in gpio_save()
82 	for (uint32_t i = 0U; i < 4U; i++) {  in gpio_restore()  local
83 		mmio_write_32(ctx->base + gpio_ctrl_offset[i], 0x0);  in gpio_restore()
86 	for (uint32_t i = 0U; i < ctx->pin_num; i++) {  in gpio_restore()  local
87 		mmio_write_32(ctx->base + 0x80 + i * 4U, ctx->gpio_icr[i]);  in gpio_restore()
90 	for (uint32_t i = 4U; i < GPIO_CTRL_REG_NUM; i++)  in gpio_restore()  local
91 		mmio_write_32(ctx->base + gpio_ctrl_offset[i], ctx->port_ctrl[i]);  in gpio_restore()
94 	for (uint32_t i = 0U; i < 4U; i++) {  in gpio_restore()  local
95 		mmio_write_32(ctx->base + gpio_ctrl_offset[i], ctx->port_ctrl[i]);  in gpio_restore()
150 	for (uint32_t i = 0U; i < ARRAY_SIZE(per_hsk_cfg); i++) {  in peripheral_qchannel_hsk()  local
151 		if (active_wakeup_irq(per_hsk_cfg[i].wakeup_irq)) {  in peripheral_qchannel_hsk()
152 			per_lpm[num_hsks].perId = per_hsk_cfg[i].per_idx;  in peripheral_qchannel_hsk()
168 	for (uint32_t i = 0U; i < IMR_NUM; i++) {  in imx_set_sys_wakeup()  local
171 			irq_mask[i] =  in imx_set_sys_wakeup()
172 				~gicd_read_isenabler(gicd_base, 32 * (i + 1));  in imx_set_sys_wakeup()
174 			irq_mask[i] = 0xFFFFFFFF;  in imx_set_sys_wakeup()
177 		if (~irq_mask[i] & wakeup_irq_mask[i]) {  in imx_set_sys_wakeup()
178 			if (i == IRQ_MASK(NETC_IREC_PCI_INT_X0) &&  in imx_set_sys_wakeup()
179 			    (wakeup_irq_mask[i] & IRQ_SHIFT(NETC_IREC_PCI_INT_X0))) {  in imx_set_sys_wakeup()
204 	for (uint32_t i = 0U; i < GPIO_NUM; i++) {  in imx9_sys_sleep_prepare()  local
205 		gpio_save(&gpios[i]);  in imx9_sys_sleep_prepare()
209 	for (uint32_t i = 0U; i < WDOG_NUM; i++) {  in imx9_sys_sleep_prepare()  local
210 		wdog_save(&wdogs[i]);  in imx9_sys_sleep_prepare()
230 	for (uint32_t i = 0U; i < GPIO_NUM; i++) {  in imx9_sys_sleep_unprepare()  local
231 		gpio_restore(&gpios[i]);  in imx9_sys_sleep_unprepare()
235 	for (uint32_t i = 0U; i < WDOG_NUM; i++) {  in imx9_sys_sleep_unprepare()  local
236 		wdog_restore(&wdogs[i]);  in imx9_sys_sleep_unprepare()