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Searched refs:flush_dcache_range (Results 1 – 25 of 114) sorted by relevance

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/rk3399_ARM-atf/plat/socionext/uniphier/
H A Duniphier_psci.c39 flush_dcache_range((uint64_t)&uniphier_holding_pen_release, in uniphier_psci_pwr_domain_on()
71 flush_dcache_range((uint64_t)&uniphier_holding_pen_release, in uniphier_psci_pwr_domain_pwr_down_wfi()
125 flush_dcache_range((uint64_t)&uniphier_sec_entrypoint, in plat_setup_psci_ops()
161 flush_dcache_range((uint64_t)&uniphier_psci_scp_mode, in uniphier_psci_init()
/rk3399_ARM-atf/bl1/aarch32/
H A Dbl1_context_mgmt.c88 flush_dcache_range((uintptr_t)&bl1_next_smc_context_ptr, in flush_smc_and_cpu_ctx()
90 flush_dcache_range((uintptr_t)bl1_next_smc_context_ptr, in flush_smc_and_cpu_ctx()
93 flush_dcache_range((uintptr_t)&bl1_next_cpu_context_ptr, in flush_smc_and_cpu_ctx()
95 flush_dcache_range((uintptr_t)bl1_next_cpu_context_ptr, in flush_smc_and_cpu_ctx()
/rk3399_ARM-atf/plat/amlogic/gxbb/
H A Dgxbb_pm.c36 flush_dcache_range(cpu_mailbox_addr, sizeof(uint64_t)); in gxbb_program_mailbox()
94 flush_dcache_range((uintptr_t)&gxbb_cpu0_go, sizeof(gxbb_cpu0_go)); in gxbb_pwr_domain_on()
121 flush_dcache_range((uintptr_t)&gxbb_cpu0_go, sizeof(gxbb_cpu0_go)); in gxbb_pwr_domain_on_finish()
137 flush_dcache_range(addr, sizeof(uint32_t)); in gxbb_pwr_domain_off()
/rk3399_ARM-atf/plat/nvidia/tegra/drivers/bpmp/
H A Dbpmp.c169 flush_dcache_range((uint64_t)channel_base, in tegra_bpmp_init()
171 flush_dcache_range((uint64_t)&bpmp_init_state, in tegra_bpmp_init()
195 flush_dcache_range((uint64_t)&bpmp_init_state, in tegra_bpmp_suspend()
225 flush_dcache_range((uint64_t)&bpmp_init_state, in tegra_bpmp_resume()
/rk3399_ARM-atf/plat/arm/board/arm_fpga/
H A Dfpga_pm.c55 flush_dcache_range((uintptr_t)&hold_base[pos], sizeof(uint64_t)); in fpga_pwr_domain_on()
99 flush_dcache_range((uint64_t)&fpga_sec_entrypoint, in plat_setup_psci_ops()
/rk3399_ARM-atf/plat/arm/board/n1sdp/
H A Dn1sdp_bl2_setup.c41 flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE); in dmc_ecc_setup()
43 flush_dcache_range(ARM_DRAM2_BASE, dram2_size); in dmc_ecc_setup()
H A Dn1sdp_bl31_setup.c103 flush_dcache_range(N1SDP_REMOTE_DRAM1_BASE, N1SDP_REMOTE_DRAM1_SIZE); in remote_dmc_ecc_setup()
105 flush_dcache_range(N1SDP_REMOTE_DRAM2_BASE, remote_dram2_size); in remote_dmc_ecc_setup()
/rk3399_ARM-atf/plat/marvell/armada/common/mss/
H A Dmss_ipc_drv.c64 flush_dcache_range((uint64_t)&msg_index, sizeof(msg_index)); in mv_pm_ipc_queue_addr_get()
99 flush_dcache_range((uint64_t)&msg_sync, sizeof(msg_sync)); in mv_pm_ipc_msg_tx()
/rk3399_ARM-atf/drivers/nxp/crypto/caam/src/auth/
H A Drsa.c59 flush_dcache_range((uintptr_t)sign, klen); in rsa_public_verif_sec()
60 flush_dcache_range((uintptr_t)rsa_pub_key, 2 * klen); in rsa_public_verif_sec()
61 flush_dcache_range((uintptr_t)&ctx.pkin, sizeof(ctx.pkin)); in rsa_public_verif_sec()
H A Dhash.c83 flush_dcache_range((uintptr_t)data_ptr, data_len); in hash_update()
140 flush_dcache_range((uintptr_t)ctx->sg_tbl, in hash_final()
/rk3399_ARM-atf/drivers/nxp/crypto/caam/src/
H A Dsec_jr_driver.c56 flush_dcache_range((uintptr_t)(job_ring->input_ring), in init_job_ring()
58 flush_dcache_range((uintptr_t)(job_ring->output_ring), in init_job_ring()
225 flush_dcache_range((uintptr_t)(&job_ring->input_ring[job_ring->pidx]), in enq_jr_desc()
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/topology/default/
H A Dpwr.c71 flush_dcache_range( in pwr_domain_coordination()
113 flush_dcache_range( in pwr_domain_coordination()
/rk3399_ARM-atf/plat/arm/board/fvp/
H A Dfvp_bl2_measured_boot.c223 flush_dcache_range((uintptr_t)secure_tl, secure_tl->size); in bl2_plat_mboot_finish()
250 flush_dcache_range(ARM_EVENT_LOG_DRAM1_BASE, event_log_cur_size); in bl2_plat_mboot_finish()
276 flush_dcache_range(ns_log_addr, event_log_cur_size); in bl2_plat_mboot_finish()
/rk3399_ARM-atf/plat/socionext/synquacer/
H A Dsq_psci.c204 flush_dcache_range((uint64_t)sq_sec_ep, in plat_setup_psci_ops()
208 flush_dcache_range((uint64_t)&sq_sec_entrypoint, in plat_setup_psci_ops()
/rk3399_ARM-atf/plat/qemu/common/trp/
H A Dqemu_trp_setup.c33 flush_dcache_range((uintptr_t)manifest, sizeof(struct rmm_manifest)); in qemu_trp_process_manifest()
/rk3399_ARM-atf/lib/aarch32/
H A Dcache_helpers.S10 .globl flush_dcache_range symbol
45 func flush_dcache_range
47 endfunc flush_dcache_range
/rk3399_ARM-atf/plat/hisilicon/hikey960/
H A Dhikey960_mcu_load.c45 flush_dcache_range((uintptr_t)HISI_RESERVED_MEM_BASE, in load_lpm3()
/rk3399_ARM-atf/plat/marvell/armada/common/
H A Dmarvell_pm.c41 flush_dcache_range((uintptr_t)PLAT_MARVELL_MAILBOX_BASE + in marvell_program_mailbox()
/rk3399_ARM-atf/plat/brcm/board/common/
H A Dbcm_elog_ddr.c119 flush_dcache_range((uintptr_t)&setup, sizeof(struct elog_setup)); in elog_init_ddr_log()
120 flush_dcache_range((uintptr_t)setup.params[0], setup.params[1]); in elog_init_ddr_log()
/rk3399_ARM-atf/plat/intel/soc/common/sip/
H A Dsocfpga_sip_fcs.c75 flush_dcache_range((uintptr_t)cmd->cb_args, resp->rcvd_resp_len * MBOX_WORD_BYTE); in fcs_get_attest_cert_cb()
127 flush_dcache_range((uintptr_t)cmd->cb_args, resp->rcvd_resp_len * MBOX_WORD_BYTE); in fcs_cs_get_digest_cb()
149 flush_dcache_range((uintptr_t)cmd->cb_args, resp->rcvd_resp_len * MBOX_WORD_BYTE); in fcs_cs_mac_verify_cb()
169 flush_dcache_range((uintptr_t)cmd->cb_args, resp->rcvd_resp_len * MBOX_WORD_BYTE); in fcs_cs_hash_sign_req_cb()
189 flush_dcache_range((uintptr_t)cmd->cb_args, resp->rcvd_resp_len * MBOX_WORD_BYTE); in fcs_cs_hash_sig_verify_req_cb()
230 flush_dcache_range((uintptr_t)cmd->cb_args, resp->rcvd_resp_len * MBOX_WORD_BYTE); in fcs_cs_data_sign_req_cb()
267 flush_dcache_range((uintptr_t)cmd->cb_args, resp->rcvd_resp_len * MBOX_WORD_BYTE); in fcs_cs_get_public_key_cb()
286 flush_dcache_range((uintptr_t)cmd->cb_args, resp->rcvd_resp_len * MBOX_WORD_BYTE); in fcs_cs_data_sig_verify_req_cb()
306 flush_dcache_range((uintptr_t)cmd->cb_args, resp->rcvd_resp_len * MBOX_WORD_BYTE); in fcs_cs_ecdh_request_cb()
372 flush_dcache_range(addr - *ret_size, *ret_size); in intel_fcs_random_number_gen()
[all …]
/rk3399_ARM-atf/plat/arm/board/morello/
H A Dmorello_bl2_setup.c41 flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE); in dmc_ecc_setup()
46 flush_dcache_range(ARM_DRAM2_BASE, dram2_size); in dmc_ecc_setup()
/rk3399_ARM-atf/plat/amlogic/gxl/
H A Dgxl_pm.c109 flush_dcache_range((uintptr_t)&gxl_cpu0_go, in gxl_pwr_domain_on()
137 flush_dcache_range((uintptr_t)&gxl_cpu0_go, in gxl_pwr_domain_on_finish()
/rk3399_ARM-atf/plat/amlogic/g12a/
H A Dg12a_pm.c109 flush_dcache_range((uintptr_t)&g12a_cpu0_go, in g12a_pwr_domain_on()
137 flush_dcache_range((uintptr_t)&g12a_cpu0_go, in g12a_pwr_domain_on_finish()
/rk3399_ARM-atf/plat/arm/common/trp/
H A Darm_trp_setup.c41 flush_dcache_range((uintptr_t)manifest, sizeof(struct rmm_manifest)); in arm_trp_process_manifest()
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv3_2/
H A Dmt_cpu_pm.c228 flush_dcache_range((uintptr_t)&mt_pwr_nodes[MT_PWR_NONMCUSYS], in cpupm_do_pstate_off()
239 flush_dcache_range((uintptr_t)&mt_pwr_nodes[MT_PWR_MCUSYS_PDN], in cpupm_do_pstate_off()
269 flush_dcache_range((uintptr_t)&mt_pwr_nodes[MT_PWR_MCUSYS_PDN], in cpupm_do_pstate_on()
301 flush_dcache_range((uintptr_t)&mt_pwr_nodes[MT_PWR_NONMCUSYS], in cpupm_do_pstate_on()

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