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Searched refs:ddr_data (Results 1 – 6 of 6) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/px30/drivers/pmu/
H A Dpmu.c102 static struct px30_sleep_ddr_data ddr_data variable
184 SAVE_QOS(ddr_data.cpu_qos, CPU); in qos_save()
187 SAVE_QOS(ddr_data.gpu_qos, GPU); in qos_save()
189 SAVE_QOS(ddr_data.isp_128m_qos, ISP_128M); in qos_save()
190 SAVE_QOS(ddr_data.isp_rd_qos, ISP_RD); in qos_save()
191 SAVE_QOS(ddr_data.isp_wr_qos, ISP_WR); in qos_save()
192 SAVE_QOS(ddr_data.isp_m1_qos, ISP_M1); in qos_save()
193 SAVE_QOS(ddr_data.vip_qos, VIP); in qos_save()
196 SAVE_QOS(ddr_data.rga_rd_qos, RGA_RD); in qos_save()
197 SAVE_QOS(ddr_data.rga_wr_qos, RGA_WR); in qos_save()
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/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/
H A Dpmu.c97 static struct rk3588_sleep_ddr_data ddr_data; variable
594 ddr_data.qch_pwr_st = in pmu_power_domains_suspend()
596 ddr_data.pmu_pd_st0 = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(0)); in pmu_power_domains_suspend()
597 ddr_data.bus_idle_st0 = mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST(0)); in pmu_power_domains_suspend()
601 if ((ddr_data.pmu_pd_st0 & BIT(PD_PHP)) == 0) in pmu_power_domains_suspend()
604 if ((ddr_data.pmu_pd_st0 & BIT(PD_CRYPTO)) == 0) in pmu_power_domains_suspend()
666 pmu_set_power_domain(PD_CRYPTO, !!(ddr_data.pmu_pd_st0 & BIT(PD_CRYPTO))); in pmu_power_domains_resume()
667 pmu_set_power_domain(PD_SDMMC, !!(ddr_data.pmu_pd_st0 & BIT(PD_SDMMC))); in pmu_power_domains_resume()
669 pmu_set_power_domain(PD_NVM, !!(ddr_data.pmu_pd_st0 & BIT(PD_NVM))); in pmu_power_domains_resume()
670 pmu_set_power_domain(PD_NVM0, !!(ddr_data.pmu_pd_st0 & BIT(PD_NVM0))); in pmu_power_domains_resume()
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/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/pmu/
H A Dpmu.c42 static struct rk3576_sleep_ddr_data ddr_data; variable
541 ddr_data.pmu_pd_st = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST); in pmu_power_domains_suspend()
542 ddr_data.bus_idle_st = mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST); in pmu_power_domains_suspend()
543 ddr_data.pmu2_pwrgt_sft_con0 = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_SFTCON(0)); in pmu_power_domains_suspend()
549 if ((ddr_data.pmu_pd_st & BIT(pmu_pd_php)) == 0) in pmu_power_domains_suspend()
562 pmu_set_power_domain(i, !!(ddr_data.pmu_pd_st & BIT(i))); in pmu_power_domains_resume()
567 0x30000000 | ddr_data.pmu2_pwrgt_sft_con0); in pmu_power_domains_resume()
570 pmu_bus_idle_req(i, !!(ddr_data.bus_idle_st & BIT(i))); in pmu_power_domains_resume()
572 if ((ddr_data.pmu_pd_st & BIT(pmu_pd_php)) == 0) in pmu_power_domains_resume()
582 ddr_data.ddrgrf_cha_con2 = in ddr_sleep_config()
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/rk3399_ARM-atf/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c28 static struct rk3328_sleep_ddr_data ddr_data; variable
254 ddr_data.clk_ungt_save[i] = in clks_gating_suspend()
267 ddr_data.clk_ungt_save[i] | 0xffff0000); in clks_gating_resume()
349 ddr_data.cru_plls_con_save[pll_id][i] = in pll_suspend()
359 ddr_data.cru_plls_con_save[pll_id][1] | 0xc0000000); in pll_resume()
363 if (PLL_IS_NORM_MODE(ddr_data.cru_mode_save, pll_id)) in pll_resume()
370 ddr_data.cru_mode_save = mmio_read_32(CRU_BASE + CRU_CRU_MODE); in pm_plls_suspend()
371 ddr_data.clk_sel0 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(0)); in pm_plls_suspend()
372 ddr_data.clk_sel1 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(1)); in pm_plls_suspend()
373 ddr_data.clk_sel18 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(18)); in pm_plls_suspend()
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/rk3399_ARM-atf/plat/rockchip/common/pmusram/
H A Dcpus_on_fixed_addr.h34 uint64_t ddr_data; member
44 CASSERT(__builtin_offsetof(struct psram_data_t, ddr_data) == PSRAM_DT_DDR_DATA,
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/pmu/
H A Dpmu.c512 psram_sleep_cfg->ddr_data = (uint64_t)0; in plat_rockchip_pmu_init()