42 static struct rk3576_sleep_ddr_data ddr_data;  variable
541 	ddr_data.pmu_pd_st = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST);  in pmu_power_domains_suspend()
542 	ddr_data.bus_idle_st = mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST);  in pmu_power_domains_suspend()
543 	ddr_data.pmu2_pwrgt_sft_con0 = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_SFTCON(0));  in pmu_power_domains_suspend()
549 	if ((ddr_data.pmu_pd_st & BIT(pmu_pd_php)) == 0)  in pmu_power_domains_suspend()
562 		pmu_set_power_domain(i, !!(ddr_data.pmu_pd_st & BIT(i)));  in pmu_power_domains_resume()
567 		      0x30000000 | ddr_data.pmu2_pwrgt_sft_con0);  in pmu_power_domains_resume()
570 		pmu_bus_idle_req(i, !!(ddr_data.bus_idle_st & BIT(i)));  in pmu_power_domains_resume()
572 	if ((ddr_data.pmu_pd_st & BIT(pmu_pd_php)) == 0)  in pmu_power_domains_resume()
582 	ddr_data.ddrgrf_cha_con2 =  in ddr_sleep_config()
584 	ddr_data.ddrgrf_chb_con2 =  in ddr_sleep_config()
594 		      WITH_16BITS_WMSK(ddr_data.ddrgrf_cha_con2));  in ddr_sleep_config_restore()
596 		      WITH_16BITS_WMSK(ddr_data.ddrgrf_chb_con2));  in ddr_sleep_config_restore()
615 	uint32_t key_upd_msk = ddr_data.pmu_pd_st & BIT(pmu_pd_vop) ? 0x3 : 0x7;  in pmu_sleep_config()
616 	uint32_t fw_lkp_upd_msk = ddr_data.pmu_pd_st & BIT(pmu_pd_npu) ? 0x3 : 0x7;  in pmu_sleep_config()
621 	ddr_data.pmu2_bisr_glb_con = mmio_read_32(PMU_BASE + PMU2_BISR_GLB_CON);  in pmu_sleep_config()
623 	ddr_data.pmu2_fast_pwr_con =  in pmu_sleep_config()
626 	ddr_data.pmu2_c0_ack_sel_con0 =  in pmu_sleep_config()
628 	ddr_data.pmu2_c1_ack_sel_con0 =  in pmu_sleep_config()
630 	ddr_data.pmu2_c2_ack_sel_con0 =  in pmu_sleep_config()
632 	ddr_data.pmu0grf_soc_con5 =  in pmu_sleep_config()
817 		      WITH_16BITS_WMSK(ddr_data.pmu2_fast_pwr_con));  in pmu_sleep_restore()
819 		      WITH_16BITS_WMSK(ddr_data.pmu2_bisr_glb_con));  in pmu_sleep_restore()
822 		      WITH_16BITS_WMSK(ddr_data.pmu2_c0_ack_sel_con0));  in pmu_sleep_restore()
824 		      WITH_16BITS_WMSK(ddr_data.pmu2_c1_ack_sel_con0));  in pmu_sleep_restore()
826 		      WITH_16BITS_WMSK(ddr_data.pmu2_c2_ack_sel_con0));  in pmu_sleep_restore()
829 		      WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con5));  in pmu_sleep_restore()
834 	ddr_data.sys_sgrf_soc_con0 =  in secure_watchdog_disable()
845 		      ddr_data.sys_sgrf_soc_con0 |  in secure_watchdog_restore()
854 	ddr_data.pmu0grf_soc_con0 =  in soc_sleep_config()
856 	ddr_data.pmu0grf_soc_con1 =  in soc_sleep_config()
859 	ddr_data.gpio0a_iomux_l =  in soc_sleep_config()
861 	ddr_data.gpio0a_iomux_h =  in soc_sleep_config()
863 	ddr_data.gpio0b_iomux_l =  in soc_sleep_config()
879 		      WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_l));  in soc_sleep_restore()
881 		      WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_h));  in soc_sleep_restore()
883 		      WITH_16BITS_WMSK(ddr_data.gpio0b_iomux_l));  in soc_sleep_restore()
886 		      WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con1));  in soc_sleep_restore()
888 		      WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con0));  in soc_sleep_restore()
893 	ddr_data.cru_mode_con = mmio_read_32(CRU_BASE + 0x280);  in pm_pll_suspend()
894 	ddr_data.secure_cru_mode = mmio_read_32(SECURE_CRU_BASE + 0x4280);  in pm_pll_suspend()
907 	mmio_write_32(CRU_BASE + 0x280, WITH_16BITS_WMSK(ddr_data.cru_mode_con));  in pm_pll_restore()
909 		      WITH_16BITS_WMSK(ddr_data.secure_cru_mode));  in pm_pll_restore()
1030 	psram_sleep_cfg->ddr_data = 0;  in plat_rockchip_pmu_init()