Lines Matching refs:ddr_data
97 static struct rk3588_sleep_ddr_data ddr_data; variable
594 ddr_data.qch_pwr_st = in pmu_power_domains_suspend()
596 ddr_data.pmu_pd_st0 = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(0)); in pmu_power_domains_suspend()
597 ddr_data.bus_idle_st0 = mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST(0)); in pmu_power_domains_suspend()
601 if ((ddr_data.pmu_pd_st0 & BIT(PD_PHP)) == 0) in pmu_power_domains_suspend()
604 if ((ddr_data.pmu_pd_st0 & BIT(PD_CRYPTO)) == 0) in pmu_power_domains_suspend()
666 pmu_set_power_domain(PD_CRYPTO, !!(ddr_data.pmu_pd_st0 & BIT(PD_CRYPTO))); in pmu_power_domains_resume()
667 pmu_set_power_domain(PD_SDMMC, !!(ddr_data.pmu_pd_st0 & BIT(PD_SDMMC))); in pmu_power_domains_resume()
669 pmu_set_power_domain(PD_NVM, !!(ddr_data.pmu_pd_st0 & BIT(PD_NVM))); in pmu_power_domains_resume()
670 pmu_set_power_domain(PD_NVM0, !!(ddr_data.pmu_pd_st0 & BIT(PD_NVM0))); in pmu_power_domains_resume()
672 pmu_set_power_domain(PD_SDIO, !!(ddr_data.pmu_pd_st0 & BIT(PD_SDIO))); in pmu_power_domains_resume()
674 pmu_set_power_domain(PD_PHP, !!(ddr_data.pmu_pd_st0 & BIT(PD_PHP))); in pmu_power_domains_resume()
675 pmu_set_power_domain(PD_PCIE, !!(ddr_data.pmu_pd_st0 & BIT(PD_PCIE))); in pmu_power_domains_resume()
676 pmu_set_power_domain(PD_GMAC, !!(ddr_data.pmu_pd_st0 & BIT(PD_GMAC))); in pmu_power_domains_resume()
678 pmu_set_power_domain(PD_AUDIO, !!(ddr_data.pmu_pd_st0 & BIT(PD_AUDIO))); in pmu_power_domains_resume()
680 pmu_set_power_domain(PD_USB, !!(ddr_data.pmu_pd_st0 & BIT(PD_USB))); in pmu_power_domains_resume()
682 pmu_set_power_domain(PD_RGA31, !!(ddr_data.pmu_pd_st0 & BIT(PD_RGA31))); in pmu_power_domains_resume()
684 pmu_set_power_domain(PD_VI, !!(ddr_data.pmu_pd_st0 & BIT(PD_VI))); in pmu_power_domains_resume()
685 pmu_set_power_domain(PD_ISP1, !!(ddr_data.pmu_pd_st0 & BIT(PD_ISP1))); in pmu_power_domains_resume()
686 pmu_set_power_domain(PD_FEC, !!(ddr_data.pmu_pd_st0 & BIT(PD_FEC))); in pmu_power_domains_resume()
688 pmu_set_power_domain(PD_VOP, !!(ddr_data.pmu_pd_st0 & BIT(PD_VOP))); in pmu_power_domains_resume()
690 pmu_set_power_domain(PD_VO1, !!(ddr_data.pmu_pd_st0 & BIT(PD_VO1))); in pmu_power_domains_resume()
692 pmu_set_power_domain(PD_VO0, !!(ddr_data.pmu_pd_st0 & BIT(PD_VO0))); in pmu_power_domains_resume()
694 pmu_set_power_domain(PD_VDPU, !!(ddr_data.pmu_pd_st0 & BIT(PD_VDPU))); in pmu_power_domains_resume()
695 pmu_set_power_domain(PD_AV1, !!(ddr_data.pmu_pd_st0 & BIT(PD_AV1))); in pmu_power_domains_resume()
696 pmu_set_power_domain(PD_RGA30, !!(ddr_data.pmu_pd_st0 & BIT(PD_RGA30))); in pmu_power_domains_resume()
698 pmu_set_power_domain(PD_VCODEC, !!(ddr_data.pmu_pd_st0 & BIT(PD_VCODEC))); in pmu_power_domains_resume()
699 pmu_set_power_domain(PD_VENC0, !!(ddr_data.pmu_pd_st0 & BIT(PD_VENC0))); in pmu_power_domains_resume()
700 pmu_set_power_domain(PD_VENC1, !!(ddr_data.pmu_pd_st0 & BIT(PD_VENC1))); in pmu_power_domains_resume()
701 pmu_set_power_domain(PD_RKVDEC0, !!(ddr_data.pmu_pd_st0 & BIT(PD_RKVDEC0))); in pmu_power_domains_resume()
702 pmu_set_power_domain(PD_RKVDEC1, !!(ddr_data.pmu_pd_st0 & BIT(PD_RKVDEC1))); in pmu_power_domains_resume()
704 pmu_set_power_domain(PD_NPU, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPU))); in pmu_power_domains_resume()
705 pmu_set_power_domain(PD_NPUTOP, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPUTOP))); in pmu_power_domains_resume()
706 pmu_set_power_domain(PD_NPU2, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPU2))); in pmu_power_domains_resume()
707 pmu_set_power_domain(PD_NPU1, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPU1))); in pmu_power_domains_resume()
709 pmu_set_power_domain(PD_GPU, !!(ddr_data.pmu_pd_st0 & BIT(PD_GPU))); in pmu_power_domains_resume()
712 pmu_bus_idle_req(i, !!(ddr_data.bus_idle_st0 & BIT(i))); in pmu_power_domains_resume()
714 pmu_qch_pwr_ctlr(0x10, !!(ddr_data.qch_pwr_st & 0x10)); in pmu_power_domains_resume()
715 pmu_qch_pwr_ctlr(0x8, !!(ddr_data.qch_pwr_st & 0x8)); in pmu_power_domains_resume()
716 pmu_qch_pwr_ctlr(0x4, !!(ddr_data.qch_pwr_st & 0x4)); in pmu_power_domains_resume()
717 pmu_qch_pwr_ctlr(0x2, !!(ddr_data.qch_pwr_st & 0x2)); in pmu_power_domains_resume()
718 pmu_qch_pwr_ctlr(0x1, !!(ddr_data.qch_pwr_st & 0x1)); in pmu_power_domains_resume()
719 pmu_qch_pwr_ctlr(0x40, !!(ddr_data.qch_pwr_st & 0x40)); in pmu_power_domains_resume()
720 pmu_qch_pwr_ctlr(0x20, !!(ddr_data.qch_pwr_st & 0x20)); in pmu_power_domains_resume()
722 if ((ddr_data.pmu_pd_st0 & BIT(PD_CRYPTO)) == 0) in pmu_power_domains_resume()
725 if ((ddr_data.pmu_pd_st0 & BIT(PD_PHP)) == 0) in pmu_power_domains_resume()
901 ddr_data.ddrgrf_chn_con0[0] = in ddr_sleep_config()
903 ddr_data.ddrgrf_chn_con0[1] = in ddr_sleep_config()
905 ddr_data.ddrgrf_chn_con1[0] = in ddr_sleep_config()
907 ddr_data.ddrgrf_chn_con1[1] = in ddr_sleep_config()
909 ddr_data.ddrgrf_chn_con2[0] = in ddr_sleep_config()
911 ddr_data.ddrgrf_chn_con2[1] = in ddr_sleep_config()
925 ddr_data.ddrgrf_chn_con0[2] = in ddr_sleep_config()
927 ddr_data.ddrgrf_chn_con0[3] = in ddr_sleep_config()
929 ddr_data.ddrgrf_chn_con1[2] = in ddr_sleep_config()
931 ddr_data.ddrgrf_chn_con1[3] = in ddr_sleep_config()
933 ddr_data.ddrgrf_chn_con2[2] = in ddr_sleep_config()
935 ddr_data.ddrgrf_chn_con2[3] = in ddr_sleep_config()
949 ddr_data.pmu1_ddr_pwr_sft_con[i] = in ddr_sleep_config()
961 0x0fff0000 | ddr_data.pmu1_ddr_pwr_sft_con[i]); in ddr_sleep_config_restore()
966 0x00400000 | ddr_data.ddrgrf_chn_con1[0]); in ddr_sleep_config_restore()
968 0x00400000 | ddr_data.ddrgrf_chn_con1[1]); in ddr_sleep_config_restore()
970 0x00200000 | ddr_data.ddrgrf_chn_con0[0]); in ddr_sleep_config_restore()
972 0x00200000 | ddr_data.ddrgrf_chn_con0[1]); in ddr_sleep_config_restore()
974 0x28000000 | ddr_data.ddrgrf_chn_con2[0]); in ddr_sleep_config_restore()
976 0x28000000 | ddr_data.ddrgrf_chn_con2[1]); in ddr_sleep_config_restore()
981 0x00400000 | ddr_data.ddrgrf_chn_con1[2]); in ddr_sleep_config_restore()
983 0x00400000 | ddr_data.ddrgrf_chn_con1[3]); in ddr_sleep_config_restore()
985 0x00200000 | ddr_data.ddrgrf_chn_con0[2]); in ddr_sleep_config_restore()
987 0x00200000 | ddr_data.ddrgrf_chn_con0[3]); in ddr_sleep_config_restore()
989 0x28000000 | ddr_data.ddrgrf_chn_con2[2]); in ddr_sleep_config_restore()
991 0x28000000 | ddr_data.ddrgrf_chn_con2[3]); in ddr_sleep_config_restore()
1004 ddr_data.pmu1grf_soc_con7 = mmio_read_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(7)); in pmu_sleep_config()
1005 ddr_data.pmu1grf_soc_con8 = mmio_read_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(8)); in pmu_sleep_config()
1006 ddr_data.pmu1grf_soc_con9 = mmio_read_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(9)); in pmu_sleep_config()
1007 ddr_data.pmu1sgrf_soc_con14 = mmio_read_32(PMU1SGRF_BASE + PMU1_SGRF_SOC_CON(14)); in pmu_sleep_config()
1008 ddr_data.pmu0sgrf_soc_con1 = mmio_read_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(1)); in pmu_sleep_config()
1009 ddr_data.pmu0grf_soc_con1 = mmio_read_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(1)); in pmu_sleep_config()
1011 ddr_data.pmu2_vol_gate_con[0] = mmio_read_32(PMU_BASE + PMU2_VOL_GATE_CON(0)); in pmu_sleep_config()
1012 ddr_data.pmu2_vol_gate_con[1] = mmio_read_32(PMU_BASE + PMU2_VOL_GATE_CON(1)); in pmu_sleep_config()
1013 ddr_data.pmu2_vol_gate_con[2] = mmio_read_32(PMU_BASE + PMU2_VOL_GATE_CON(2)); in pmu_sleep_config()
1015 ddr_data.pmu2_submem_gate_sft_con0 = in pmu_sleep_config()
1019 ddr_data.gpio0a_iomux_l = mmio_read_32(PMU0IOC_BASE + 0); in pmu_sleep_config()
1020 ddr_data.gpio0a_iomux_h = mmio_read_32(PMU0IOC_BASE + 4); in pmu_sleep_config()
1021 ddr_data.pmu0grf_soc_con3 = mmio_read_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(3)); in pmu_sleep_config()
1197 WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con7)); in pmu_sleep_restore()
1199 WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con8)); in pmu_sleep_restore()
1201 WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con9)); in pmu_sleep_restore()
1203 WITH_16BITS_WMSK(ddr_data.pmu1sgrf_soc_con14)); in pmu_sleep_restore()
1206 WITH_16BITS_WMSK(ddr_data.pmu0sgrf_soc_con1)); in pmu_sleep_restore()
1208 WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con1)); in pmu_sleep_restore()
1226 WITH_16BITS_WMSK(ddr_data.pmu2_vol_gate_con[0])); in pmu_sleep_restore()
1228 WITH_16BITS_WMSK(ddr_data.pmu2_vol_gate_con[1])); in pmu_sleep_restore()
1230 WITH_16BITS_WMSK(ddr_data.pmu2_vol_gate_con[2])); in pmu_sleep_restore()
1233 WITH_16BITS_WMSK(ddr_data.pmu2_submem_gate_sft_con0)); in pmu_sleep_restore()
1236 WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con3)); in pmu_sleep_restore()
1238 WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con2)); in pmu_sleep_restore()
1241 WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_h)); in pmu_sleep_restore()
1243 WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_l)); in pmu_sleep_restore()
1248 ddr_data.gpio0b_iomux_l = mmio_read_32(PMU0IOC_BASE + 0x8); in soc_sleep_config()
1259 mmio_write_32(PMU0IOC_BASE + 0x8, WITH_16BITS_WMSK(ddr_data.gpio0b_iomux_l)); in soc_sleep_restore()
1264 ddr_data.cru_mode_con = mmio_read_32(CRU_BASE + 0x280); in pm_pll_suspend()
1265 ddr_data.busscru_mode_con = mmio_read_32(BUSSCRU_BASE + 0x280); in pm_pll_suspend()
1266 ddr_data.pmu2_bisr_con0 = mmio_read_32(PMU_BASE + PMU2_BISR_CON(0)); in pm_pll_suspend()
1267 ddr_data.cpll_con0 = mmio_read_32(CRU_BASE + CRU_PLLS_CON(2, 0)); in pm_pll_suspend()
1268 ddr_data.pmu1cru_clksel_con1 = mmio_read_32(PMU1CRU_BASE + CRU_CLKSEL_CON(1)); in pm_pll_suspend()
1280 mmio_write_32(CRU_BASE + 0x280, WITH_16BITS_WMSK(ddr_data.cru_mode_con)); in pm_pll_restore()
1281 mmio_write_32(BUSSCRU_BASE + 0x280, WITH_16BITS_WMSK(ddr_data.busscru_mode_con)); in pm_pll_restore()
1282 mmio_write_32(CRU_BASE + CRU_PLLS_CON(2, 0), WITH_16BITS_WMSK(ddr_data.cpll_con0)); in pm_pll_restore()
1285 mmio_write_32(PMU_BASE + PMU2_BISR_CON(0), WITH_16BITS_WMSK(ddr_data.pmu2_bisr_con0)); in pm_pll_restore()
1424 psram_sleep_cfg->ddr_data = 0; in plat_rockchip_pmu_init()