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Searched refs:_PLL1 (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/drivers/st/clk/
H A Dstm32mp1_clk.c425 _PLL1, enumerator
812 _CLK_PLL(_PLL1, PLL_1600,
1119 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); in get_clock_rate()
1122 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); in get_clock_rate()
1258 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); in get_clock_rate()
1261 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); in get_clock_rate()
1264 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); in get_clock_rate()
2201 if (!pll_conf[_PLL1].status) { in stm32mp1_clk_init()
2203 pll_conf[_PLL1].cfg, &pll_conf[_PLL1].frac); in stm32mp1_clk_init()
2208 pll_conf[_PLL1].status = true; in stm32mp1_clk_init()
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H A Dclk-stm32mp2.c926 _PLL1, enumerator
958 CLK_PLL_CFG(_PLL1, _CK_PLL1, A35_SS_CHGCLKREQ),
1477 CLK_PLL1(_CK_PLL1, PLL1_CK, MUX(MUX_MUXSEL5), _PLL1, 0),
2100 if (pll_idx == _PLL1) { in clk_stm32_pll_init()
2115 for (i = _PLL1; i < _PLL_NB; i++) { in stm32mp2_clk_pll_configure()
2626 for (i = _PLL1; i < pdata->npll; i++) { in stm32_clk_parse_fdt_all_pll()
H A Dclk-stm32mp13.c867 _PLL1, enumerator
1435 struct stm32_pll_dt_cfg *pll1 = clk_stm32_pll_get_pdata(_PLL1); in clk_compute_pll1_settings()
1680 err = clk_stm32_pll_init(priv, _PLL1); in stm32_clk_pll_configure()
1939 CLK_PLL_CFG(_PLL1, _CK_PLL1, PLL_2000, RCC_PLL1CR),
2136 CLK_PLL(_CK_PLL1, PLL1, MUX(MUX_PLL12), GATE_PLL1, _PLL1, 0),