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Searched refs:SSPM_CFGREG_BASE (Results 1 – 7 of 7) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/mt8183/include/
H A Dsspm_reg.h12 #define SSPM_CFGREG_RSV_RW_REG0 (SSPM_CFGREG_BASE + 0x0100)
13 #define SSPM_CFGREG_ACAO_INT_SET (SSPM_CFGREG_BASE + 0x00D8)
14 #define SSPM_CFGREG_ACAO_INT_CLR (SSPM_CFGREG_BASE + 0x00DC)
15 #define SSPM_CFGREG_ACAO_WAKEUP_EN (SSPM_CFGREG_BASE + 0x0204)
H A Dplatform_def.h37 #define SSPM_CFGREG_BASE (IO_PHYS + 0x440000) macro
/rk3399_ARM-atf/plat/mediatek/mt8186/include/
H A Dsspm_reg.h12 #define SSPM_CFGREG_ADDR(ofs) (SSPM_CFGREG_BASE + (ofs))
H A Dplatform_def.h30 #define SSPM_CFGREG_BASE (IO_PHYS + 0x00440000) /* SSPM view: 0x30040000 */ macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/version/notifier/v4/
H A Dmt_spm_sspm_intc.h18 #define SSPM_CFGREG_ADDR(ofs) (SSPM_CFGREG_BASE + (ofs))
/rk3399_ARM-atf/plat/mediatek/mt8189/include/
H A Dplatform_def.h82 #define SSPM_CFGREG_BASE (IO_PHYS + 0x0C300000 + SSPM_REG_OFFSET) macro
/rk3399_ARM-atf/plat/mediatek/mt8196/include/
H A Dplatform_def.h342 #define SSPM_CFGREG_BASE (IO_PHYS + 0x0C300000 + SSPM_REG_OFFSET) macro