| /rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spm/ |
| H A D | spm.c | 225 mmio_clrsetbits_32(PCM_CON1, PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); in spm_disable_pcm_timer() 234 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | PCM_TIMER_EN_LSB); in spm_set_wakeup_event() 257 SPM_REGWR_CFG_KEY); in spm_set_pcm_wdt() 263 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | PCM_WDT_EN_LSB); in spm_set_pcm_wdt() 266 SPM_REGWR_CFG_KEY); in spm_set_pcm_wdt()
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| H A D | spm_pmic_wrap.c | 130 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | in mt_spm_pmic_wrap_set_phase() 152 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | in mt_spm_pmic_wrap_set_cmd()
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| H A D | spm.h | 2250 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) macro
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| /rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/ |
| H A D | mt_spm_internal.c | 315 mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); in __spm_disable_pcm_timer() 324 SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB); in __spm_set_wakeup_event() 336 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB); in __spm_set_wakeup_event() 352 SPM_REGWR_CFG_KEY); in __spm_set_wakeup_event() 484 SPM_REGWR_CFG_KEY); in __spm_set_pcm_wdt() 488 SPM_REGWR_CFG_KEY); in __spm_set_pcm_wdt() 497 SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB); in __spm_set_pcm_wdt()
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| H A D | mt_spm_pmic_wrap.c | 117 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); in mt_spm_pmic_wrap_set_phase() 140 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); in mt_spm_pmic_wrap_set_cmd()
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| H A D | mt_spm_reg.h | 2858 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) macro
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| /rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/ |
| H A D | mt_spm_internal.c | 349 mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); in __spm_disable_pcm_timer() 358 SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB); in __spm_set_wakeup_event() 370 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB); in __spm_set_wakeup_event() 390 SPM_REGWR_CFG_KEY); in __spm_set_wakeup_event() 522 SPM_REGWR_CFG_KEY); in __spm_set_pcm_wdt() 526 SPM_REGWR_CFG_KEY); in __spm_set_pcm_wdt() 535 SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB); in __spm_set_pcm_wdt()
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| H A D | mt_spm_pmic_wrap.c | 117 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); in mt_spm_pmic_wrap_set_phase() 140 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); in mt_spm_pmic_wrap_set_cmd()
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| H A D | mt_spm_reg.h | 2918 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) macro
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/ |
| H A D | mt_spm_internal.c | 268 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB); in __spm_set_wakeup_event() 279 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB); in __spm_set_wakeup_event() 294 mmio_clrsetbits_32(PCM_CON1, SPM_EVENT_COUNTER_CLR_LSB, SPM_REGWR_CFG_KEY); in __spm_set_wakeup_event() 416 mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB, SPM_REGWR_CFG_KEY); in __spm_set_pcm_wdt() 422 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB); in __spm_set_pcm_wdt() 424 mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB, SPM_REGWR_CFG_KEY); in __spm_set_pcm_wdt()
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| H A D | mt_spm_pmic_wrap.c | 119 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); in mt_spm_pmic_wrap_set_phase() 137 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); in mt_spm_pmic_wrap_set_cmd()
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| H A D | mt_spm_reg.h | 2247 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) macro
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| /rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/ |
| H A D | mt_spm_internal.c | 379 mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); in __spm_disable_pcm_timer() 389 SPM_REGWR_CFG_KEY | REG_SPM_EVENT_COUNTER_CLR_LSB); in __spm_set_wakeup_event() 401 mmio_setbits_32(PCM_CON1, (SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB)); in __spm_set_wakeup_event() 421 SPM_REGWR_CFG_KEY); in __spm_set_wakeup_event() 556 SPM_REGWR_CFG_KEY); in __spm_set_pcm_wdt() 560 SPM_REGWR_CFG_KEY); in __spm_set_pcm_wdt() 568 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB); in __spm_set_pcm_wdt()
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| H A D | mt_spm_pmic_wrap.c | 123 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); in mt_spm_pmic_wrap_set_phase() 149 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); in mt_spm_pmic_wrap_set_cmd()
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| H A D | mt_spm_reg.h | 2955 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) macro
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/ |
| H A D | mt_spm_internal.c | 127 mmio_clrsetbits_32(PCM_CON1, SPM_REGWR_CFG_KEY, REG_PCM_TIMER_EN_LSB); in __spm_reset_and_init_pcm() 131 SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB); in __spm_reset_and_init_pcm() 132 mmio_write_32(PCM_CON0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); in __spm_reset_and_init_pcm() 136 SPM_REGWR_CFG_KEY | REG_SPM_APB_INTERNAL_EN_LSB | in __spm_reset_and_init_pcm() 171 mmio_setbits_32(PCM_CON0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); in __spm_kick_im_to_fetch() 595 mmio_write_32(PCM_CON1, mmio_read_32(PCM_CON1) | SPM_REGWR_CFG_KEY | in __spm_set_wakeup_event() 659 mmio_write_32(PCM_CON0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); in __spm_kick_pcm_to_run() 768 mmio_write_32(PCM_CON1, SPM_REGWR_CFG_KEY | con1); in __spm_set_pcm_wdt() 775 con1 | SPM_REGWR_CFG_KEY | REG_PCM_WDT_EN_LSB); in __spm_set_pcm_wdt() 778 SPM_REGWR_CFG_KEY | (mmio_read_32(PCM_CON1) & in __spm_set_pcm_wdt()
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| H A D | mt_spm_reg.h | 3288 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) macro
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/ |
| H A D | mt_spm_internal.c | 629 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | REG_PCM_TIMER_EN_LSB); in __spm_set_wakeup_event() 771 SPM_REGWR_CFG_KEY); in __spm_set_pcm_wdt() 777 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | in __spm_set_pcm_wdt() 781 SPM_REGWR_CFG_KEY); in __spm_set_pcm_wdt()
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| H A D | mt_spm.c | 308 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | in mt_spm_hwctrl()
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| H A D | mt_spm_reg.h | 2097 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) macro
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| /rk3399_ARM-atf/plat/mediatek/mt8173/drivers/spm/ |
| H A D | spm.h | 114 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) macro
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| H A D | spm.c | 96 mmio_write_32(SPM_POWERON_CONFIG_SET, SPM_REGWR_CFG_KEY | SPM_REGWR_EN); in spm_register_init()
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