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Searched refs:SPM_CPU0_PWR_CON (Results 1 – 10 of 10) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/
H A Dmt_spm_internal.c87 mmio_write_32(ROOT_CORE_ADDR, SPM_CPU0_PWR_CON + (cpu * 0x4) + 0x20000000); in __spm_set_cpu_status()
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_internal.c136 root_core_addr = SPM_CPU0_PWR_CON + (cpu * 0x4); in __spm_set_cpu_status()
H A Dmt_spm_reg.h132 #define SPM_CPU0_PWR_CON (SPM_BASE + 0x20C) macro
/rk3399_ARM-atf/plat/mediatek/mt8188/include/
H A Dspm_reg.h120 #define SPM_CPU0_PWR_CON (SPM_BASE + 0x20C) macro
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_internal.c129 root_core_addr = SPM_CPU0_PWR_CON + (cpu * 0x4); in __spm_set_cpu_status()
H A Dmt_spm_reg.h127 #define SPM_CPU0_PWR_CON (SPM_BASE + 0x208) macro
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_internal.c120 root_core_addr = SPM_CPU0_PWR_CON + (cpu * 0x4); in __spm_set_cpu_status()
H A Dmt_spm_reg.h118 #define SPM_CPU0_PWR_CON (SPM_BASE + 0x208) macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_spm_reg.h84 #define SPM_CPU0_PWR_CON (SPM_BASE + 0x0268) macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm_reg.h82 #define SPM_CPU0_PWR_CON (SPM_BASE + 0x268) macro