Searched refs:PLAT_SEC_ENTRY (Results 1 – 8 of 8) sorted by relevance
| /rk3399_ARM-atf/plat/intel/soc/common/aarch64/ |
| H A D | plat_helpers.S | 40 mov_imm x0, PLAT_SEC_ENTRY
45 mov_imm x0, PLAT_SEC_ENTRY
133 mov_imm x1, PLAT_SEC_ENTRY
197 ldr x1, =PLAT_SEC_ENTRY
216 mov_imm x1, PLAT_SEC_ENTRY
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| /rk3399_ARM-atf/plat/intel/soc/common/include/ |
| H A D | platform_def.h | 128 #define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8) macro
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| /rk3399_ARM-atf/plat/intel/soc/n5x/ |
| H A D | bl31_plat_setup.c | 44 mmio_write_64(PLAT_SEC_ENTRY, 0); in bl31_early_platform_setup2()
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| /rk3399_ARM-atf/plat/intel/soc/stratix10/ |
| H A D | bl31_plat_setup.c | 52 mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY); in bl31_early_platform_setup2()
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| /rk3399_ARM-atf/plat/intel/soc/common/ |
| H A D | socfpga_psci.c | 321 mmio_write_64(PLAT_SEC_ENTRY, sec_entrypoint); in plat_setup_psci_ops()
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| /rk3399_ARM-atf/plat/intel/soc/agilex/ |
| H A D | bl31_plat_setup.c | 85 mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY); in bl31_early_platform_setup2()
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| /rk3399_ARM-atf/plat/intel/soc/agilex5/ |
| H A D | bl31_plat_setup.c | 59 mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY); in bl31_early_platform_setup2()
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| /rk3399_ARM-atf/plat/intel/soc/common/soc/ |
| H A D | socfpga_reset_manager.c | 1255 mmio_write_64(PLAT_SEC_ENTRY, entrypoint); in socfpga_cpu_reset_base()
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