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Searched refs:PCM_WDT_VAL (Results 1 – 15 of 15) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_spm.c307 mmio_write_32(PCM_WDT_VAL, 0x1); in mt_spm_hwctrl()
H A Dmt_spm_internal.c775 mmio_write_32(PCM_WDT_VAL, mmio_read_32(PCM_TIMER_VAL) + in __spm_set_pcm_wdt()
H A Dmt_spm_reg.h265 #define PCM_WDT_VAL (SPM_BASE + 0x05A8) macro
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spm/
H A Dspm.c261 mmio_write_32(PCM_WDT_VAL, in spm_set_pcm_wdt()
H A Dspm.h27 #define PCM_WDT_VAL (SPM_BASE + 0x034) macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/
H A Dmt_spm_internal.c421 mmio_write_32(PCM_WDT_VAL, mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); in __spm_set_pcm_wdt()
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_internal.c494 mmio_write_32(PCM_WDT_VAL, in __spm_set_pcm_wdt()
H A Dmt_spm_reg.h36 #define PCM_WDT_VAL (SPM_BASE + 0x034) macro
/rk3399_ARM-atf/plat/mediatek/mt8188/include/
H A Dspm_reg.h27 #define PCM_WDT_VAL (SPM_BASE + 0x034) macro
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_internal.c532 mmio_write_32(PCM_WDT_VAL, in __spm_set_pcm_wdt()
H A Dmt_spm_reg.h33 #define PCM_WDT_VAL (SPM_BASE + 0x034) macro
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_internal.c566 mmio_write_32(PCM_WDT_VAL, in __spm_set_pcm_wdt()
H A Dmt_spm_reg.h28 #define PCM_WDT_VAL (SPM_BASE + 0x034) macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm_internal.c772 mmio_write_32(PCM_WDT_VAL, in __spm_set_pcm_wdt()
H A Dmt_spm_reg.h239 #define PCM_WDT_VAL (SPM_BASE + 0x5A8) macro