| /rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spm/ |
| H A D | spm.c | 233 mmio_write_32(PCM_TIMER_VAL, val); in spm_set_wakeup_event()
259 if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) in spm_set_pcm_wdt()
260 mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX); in spm_set_pcm_wdt()
262 mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); in spm_set_pcm_wdt()
|
| H A D | spm_suspend.c | 182 settle, mmio_read_32(PCM_TIMER_VAL) / 32768, in go_to_sleep_before_wfi()
|
| H A D | spm.h | 26 #define PCM_TIMER_VAL (SPM_BASE + 0x030) macro
|
| /rk3399_ARM-atf/plat/mediatek/drivers/spm/ |
| H A D | mt_spm_dispatcher.c | 24 mmio_write_32(PCM_TIMER_VAL, time); in mt_spm_pcm_wdt()
|
| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/ |
| H A D | mt_spm_internal.c | 278 mmio_write_32(PCM_TIMER_VAL, val); in __spm_set_wakeup_event()
418 if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) { in __spm_set_pcm_wdt()
419 mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX); in __spm_set_pcm_wdt()
421 mmio_write_32(PCM_WDT_VAL, mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); in __spm_set_pcm_wdt()
|
| H A D | mt_spm_conservation.c | 66 (mmio_read_32(PCM_TIMER_VAL) / 32768)); in go_to_spm_before_wfi()
|
| /rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/ |
| H A D | mt_spm_internal.c | 335 mmio_write_32(PCM_TIMER_VAL, val); in __spm_set_wakeup_event()
490 if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) { in __spm_set_pcm_wdt()
491 mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX); in __spm_set_pcm_wdt()
495 mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); in __spm_set_pcm_wdt()
|
| H A D | mt_spm_conservation.c | 59 mmio_read_32(PCM_TIMER_VAL) / 32768); in go_to_spm_before_wfi()
|
| H A D | mt_spm_reg.h | 35 #define PCM_TIMER_VAL (SPM_BASE + 0x030) macro
|
| /rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/ |
| H A D | mt_spm_internal.c | 369 mmio_write_32(PCM_TIMER_VAL, val); in __spm_set_wakeup_event()
528 if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) { in __spm_set_pcm_wdt()
529 mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX); in __spm_set_pcm_wdt()
533 mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); in __spm_set_pcm_wdt()
|
| H A D | mt_spm_conservation.c | 61 mmio_read_32(PCM_TIMER_VAL) / 32768); in go_to_spm_before_wfi()
|
| H A D | mt_spm_reg.h | 32 #define PCM_TIMER_VAL (SPM_BASE + 0x030) macro
|
| /rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/ |
| H A D | mt_spm_internal.c | 400 mmio_write_32(PCM_TIMER_VAL, val); in __spm_set_wakeup_event()
562 if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) { in __spm_set_pcm_wdt()
563 mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX); in __spm_set_pcm_wdt()
567 mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); in __spm_set_pcm_wdt()
|
| H A D | mt_spm_conservation.c | 65 (mmio_read_32(PCM_TIMER_VAL) / 32768)); in go_to_spm_before_wfi()
|
| H A D | mt_spm_reg.h | 27 #define PCM_TIMER_VAL (SPM_BASE + 0x030) macro
|
| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/ |
| H A D | mt_spm_internal.c | 594 mmio_write_32(PCM_TIMER_VAL, val); in __spm_set_wakeup_event()
770 if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) in __spm_set_pcm_wdt()
771 mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX); in __spm_set_pcm_wdt()
773 mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); in __spm_set_pcm_wdt()
786 return mmio_read_32(PCM_TIMER_VAL) >> 15; in __spm_get_pcm_timer_val()
|
| H A D | mt_spm_reg.h | 234 #define PCM_TIMER_VAL (SPM_BASE + 0x594) macro
|
| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/ |
| H A D | mt_spm_internal.c | 628 mmio_write_32(PCM_TIMER_VAL, val); in __spm_set_wakeup_event()
773 if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) in __spm_set_pcm_wdt()
774 mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX); in __spm_set_pcm_wdt()
775 mmio_write_32(PCM_WDT_VAL, mmio_read_32(PCM_TIMER_VAL) + in __spm_set_pcm_wdt()
787 return mmio_read_32(PCM_TIMER_VAL) >> 15; in __spm_get_pcm_timer_val()
|
| H A D | mt_spm_reg.h | 260 #define PCM_TIMER_VAL (SPM_BASE + 0x0594) macro
|
| /rk3399_ARM-atf/plat/mediatek/mt8188/include/ |
| H A D | spm_reg.h | 26 #define PCM_TIMER_VAL (SPM_BASE + 0x030) macro
|