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Searched refs:PCM_CON1 (Results 1 – 16 of 16) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spm/
H A Dspm.c225 mmio_clrsetbits_32(PCM_CON1, PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); in spm_disable_pcm_timer()
234 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | PCM_TIMER_EN_LSB); in spm_set_wakeup_event()
256 mmio_clrsetbits_32(PCM_CON1, PCM_WDT_WAKE_MODE_LSB, in spm_set_pcm_wdt()
263 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | PCM_WDT_EN_LSB); in spm_set_pcm_wdt()
265 mmio_clrsetbits_32(PCM_CON1, PCM_WDT_EN_LSB, in spm_set_pcm_wdt()
H A Dspm_suspend.c180 mmio_read_32(PCM_CON1)); in go_to_sleep_before_wfi()
H A Dspm.h21 #define PCM_CON1 (SPM_BASE + 0x01C) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_internal.c315 mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); in __spm_disable_pcm_timer()
323 mmio_setbits_32(PCM_CON1, in __spm_set_wakeup_event()
336 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB); in __spm_set_wakeup_event()
351 mmio_clrsetbits_32(PCM_CON1, SPM_EVENT_COUNTER_CLR_LSB, in __spm_set_wakeup_event()
483 mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB, in __spm_set_pcm_wdt()
487 mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB, in __spm_set_pcm_wdt()
496 mmio_setbits_32(PCM_CON1, in __spm_set_pcm_wdt()
H A Dmt_spm_reg.h30 #define PCM_CON1 (SPM_BASE + 0x01C) macro
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_internal.c349 mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); in __spm_disable_pcm_timer()
357 mmio_setbits_32(PCM_CON1, in __spm_set_wakeup_event()
370 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB); in __spm_set_wakeup_event()
389 mmio_clrsetbits_32(PCM_CON1, SPM_EVENT_COUNTER_CLR_LSB, in __spm_set_wakeup_event()
521 mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB, in __spm_set_pcm_wdt()
525 mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB, in __spm_set_pcm_wdt()
534 mmio_setbits_32(PCM_CON1, in __spm_set_pcm_wdt()
H A Dmt_spm_reg.h27 #define PCM_CON1 (SPM_BASE + 0x01C) macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/
H A Dmt_spm_internal.c268 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB); in __spm_set_wakeup_event()
279 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB); in __spm_set_wakeup_event()
294 mmio_clrsetbits_32(PCM_CON1, SPM_EVENT_COUNTER_CLR_LSB, SPM_REGWR_CFG_KEY); in __spm_set_wakeup_event()
416 mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB, SPM_REGWR_CFG_KEY); in __spm_set_pcm_wdt()
422 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB); in __spm_set_pcm_wdt()
424 mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB, SPM_REGWR_CFG_KEY); in __spm_set_pcm_wdt()
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_internal.c379 mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); in __spm_disable_pcm_timer()
388 mmio_setbits_32(PCM_CON1, in __spm_set_wakeup_event()
401 mmio_setbits_32(PCM_CON1, (SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB)); in __spm_set_wakeup_event()
420 mmio_clrsetbits_32(PCM_CON1, REG_SPM_EVENT_COUNTER_CLR_LSB, in __spm_set_wakeup_event()
555 mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB, in __spm_set_pcm_wdt()
559 mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB, in __spm_set_pcm_wdt()
568 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB); in __spm_set_pcm_wdt()
H A Dmt_spm_reg.h22 #define PCM_CON1 (SPM_BASE + 0x01C) macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm_internal.c127 mmio_clrsetbits_32(PCM_CON1, SPM_REGWR_CFG_KEY, REG_PCM_TIMER_EN_LSB); in __spm_reset_and_init_pcm()
135 mmio_clrsetbits_32(PCM_CON1, REG_PCM_WDT_WAKE_LSB, in __spm_reset_and_init_pcm()
595 mmio_write_32(PCM_CON1, mmio_read_32(PCM_CON1) | SPM_REGWR_CFG_KEY | in __spm_set_wakeup_event()
767 con1 = mmio_read_32(PCM_CON1) & ~(REG_PCM_WDT_WAKE_LSB); in __spm_set_pcm_wdt()
768 mmio_write_32(PCM_CON1, SPM_REGWR_CFG_KEY | con1); in __spm_set_pcm_wdt()
774 mmio_write_32(PCM_CON1, in __spm_set_pcm_wdt()
777 mmio_write_32(PCM_CON1, in __spm_set_pcm_wdt()
778 SPM_REGWR_CFG_KEY | (mmio_read_32(PCM_CON1) & in __spm_set_pcm_wdt()
H A Dmt_spm_reg.h28 #define PCM_CON1 (SPM_BASE + 0x01C) macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_spm_internal.c629 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | REG_PCM_TIMER_EN_LSB); in __spm_set_wakeup_event()
770 mmio_clrsetbits_32(PCM_CON1, REG_PCM_WDT_WAKE_LSB, in __spm_set_pcm_wdt()
777 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | in __spm_set_pcm_wdt()
780 mmio_clrsetbits_32(PCM_CON1, REG_PCM_WDT_EN_LSB, in __spm_set_pcm_wdt()
H A Dmt_spm.c308 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | in mt_spm_hwctrl()
H A Dmt_spm_reg.h23 #define PCM_CON1 (SPM_BASE + 0x001C) macro
/rk3399_ARM-atf/plat/mediatek/mt8188/include/
H A Dspm_reg.h21 #define PCM_CON1 (SPM_BASE + 0x01C) macro