Home
last modified time | relevance | path

Searched refs:M3 (Results 1 – 11 of 11) sorted by relevance

/rk3399_ARM-atf/drivers/renesas/rcar/qos/
H A Dqos.mk13 BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c
14 BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
15 BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
29 BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c
30 BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
31 BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
70 BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c
72 BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
74 BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
76 BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
[all …]
/rk3399_ARM-atf/drivers/renesas/rcar/pfc/
H A Dpfc.mk10 BL2_SOURCES += drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
24 BL2_SOURCES += drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
53 BL2_SOURCES += drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
/rk3399_ARM-atf/docs/plat/
H A Dmeson-axg.rst5 ~1.2GHz. It also contains a Cortex-M3 used as SCP.
H A Dmeson-gxbb.rst5 1.5Ghz. It also contains a Cortex-M3 used as SCP.
H A Dmeson-g12a.rst5 ~1.8GHz. It also contains a Cortex-M3 used as SCP.
H A Dmeson-gxl.rst5 1.5Ghz. It also contains a Cortex-M3 used as SCP.
H A Drcar-gen3.rst22 | R-Car M3-W | - Salvator-X | |
25 | R-Car M3-N | - Salvator-X | |
/rk3399_ARM-atf/plat/renesas/rcar/
H A Dplatform.mk52 else ifeq (${LSI},M3)
/rk3399_ARM-atf/docs/plat/marvell/armada/
H A Dbuild.rst152 Specify path to the MSS fimware image binary which will run on Cortex-M3 coprocessor.
193 When ``CM3_SYSTEM_RESET=1``, the Cortex-M3 secure coprocessor will be used for system reset.
196 Cortex-M3 secure coprocessor.
/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/include/
H A Dddrphy_csr_all_cdefines.h6825 #define M3 0x300U macro
/rk3399_ARM-atf/docs/
H A Dchange-log.md8895 …- use PRR cut to determine DRAM size on M3 ([42ffd27](https://review.trustedfirmware.org/plugins/g…
9484 …- ddr: update DDR setting for H3, M3, M3N ([ec767c1](https://review.trustedfirmware.org/plugins/gi…
10846 setting for H3, M3, M3N, change fixed destination address of BL31 and BL32,