Searched refs:L3 (Results 1 – 6 of 6) sorted by relevance
| /rk3399_ARM-atf/plat/nvidia/tegra/include/t194/ |
| H A D | tegra194_ras_private.h | 112 X(L3, 43, 0x7B, "SNOC Interface Parity Error") \
113 X(L3, 42, 0x7A, "MCF Interface Parity Error") \
114 X(L3, 41, 0x79, "L3 Tag Parity Error") \
115 X(L3, 40, 0x78, "L3 Dir Parity Error") \
116 X(L3, 39, 0x77, "L3 Uncorrectable ECC Error") \
117 X(L3, 37, 0x75, "Multi-Hit CAM Error") \
118 X(L3, 36, 0x74, "Multi-Hit Tag Error") \
119 X(L3, 35, 0x73, "Unrecognized Command Error") \
120 X(L3, 34, 0x72, "L3 Protocol Error")
245 #define SCF_L3_BANK_RAS_NODE_LIST(X) X(L3)
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| /rk3399_ARM-atf/docs/design_documents/ |
| H A D | psci_osi_mode.rst | 674 * 8 CPUs, 1 L3 cache
682 * State3 - L3 cache off and system resources voted off
694 * State3 - L3 cache off and system resources voted off
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| /rk3399_ARM-atf/docs/plat/marvell/armada/ |
| H A D | build.rst | 93 Flag defining the LLC (L3) cache state. The cache is enabled by default (``LLC_ENABLE=1``).
97 Flag enabling the LLC (L3) cache SRAM support. The LLC SRAM is activated and used
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| /rk3399_ARM-atf/fdts/ |
| H A D | tc-base.dtsi | 582 * L3 cache in the DSU is the Memory System Component (MSC)
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| /rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/include/ |
| H A D | ddrphy_csr_all_cdefines.h | 6807 #define L3 0x300U macro
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| /rk3399_ARM-atf/docs/ |
| H A D | change-log.md | 2674 …- flush L1/L2/L3/Sys cache before HPS cold reset ([7ac7dad](https://review.trustedfirmware.org/plu…
6215 …- enable MPAM functionality of L3 DSU cache ([b45ec8c](https://review.trustedfirmware.org/plugins/…
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