Searched refs:IMR1_CORE3_A53 (Results 1 – 9 of 9) sorted by relevance
21 #define IMR1_CORE3_A53 0x1D0 macro
21 #define IMR1_CORE3_A53 0x1A8 macro
152 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0); in imx_gpc_init()
22 static uint32_t gpc_imr_offset[] = { IMR1_CORE0_A53, IMR1_CORE1_A53, IMR1_CORE2_A53, IMR1_CORE3_A53…
319 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0); in imx_gpc_init()
302 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0); in imx_gpc_init()
40 IMX_GPC_BASE + IMR1_CORE3_A53,