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Searched refs:DVFSRC_BASE (Results 1 – 10 of 10) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_spm_vcorefs_reg.h15 #define DVFSRC_BASE (IO_PHYS + 0x0C013000) macro
19 #define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0)
20 #define DVFSRC_BASIC_CONTROL_4 (DVFSRC_BASE + 0xC)
21 #define DVFSRC_SW_REQ1 (DVFSRC_BASE + 0x10)
22 #define DVFSRC_SW_REQ2 (DVFSRC_BASE + 0x14)
23 #define DVFSRC_SW_REQ3 (DVFSRC_BASE + 0x18)
24 #define DVFSRC_SW_REQ4 (DVFSRC_BASE + 0x1C)
25 #define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x20)
26 #define DVFSRC_SW_REQ6 (DVFSRC_BASE + 0x24)
27 #define DVFSRC_SW_REQ7 (DVFSRC_BASE + 0x28)
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm_vcorefs_reg.h14 #define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0)
15 #define DVFSRC_BASIC_CONTROL_2 (DVFSRC_BASE + 0x4)
16 #define DVFSRC_BASIC_CONTROL_3 (DVFSRC_BASE + 0x8)
17 #define DVFSRC_BASIC_CONTROL_4 (DVFSRC_BASE + 0xC)
18 #define DVFSRC_SW_REQ1 (DVFSRC_BASE + 0x10)
19 #define DVFSRC_SW_REQ2 (DVFSRC_BASE + 0x14)
20 #define DVFSRC_SW_REQ3 (DVFSRC_BASE + 0x18)
21 #define DVFSRC_SW_REQ4 (DVFSRC_BASE + 0x1C)
22 #define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x20)
23 #define DVFSRC_SW_REQ6 (DVFSRC_BASE + 0x24)
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_vcorefs.h72 #define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0)
73 #define DVFSRC_SW_REQ1 (DVFSRC_BASE + 0x4)
74 #define DVFSRC_SW_REQ2 (DVFSRC_BASE + 0x8)
75 #define DVFSRC_SW_REQ3 (DVFSRC_BASE + 0xC)
76 #define DVFSRC_SW_REQ4 (DVFSRC_BASE + 0x10)
77 #define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x14)
78 #define DVFSRC_SW_REQ6 (DVFSRC_BASE + 0x18)
79 #define DVFSRC_SW_REQ7 (DVFSRC_BASE + 0x1C)
80 #define DVFSRC_SW_REQ8 (DVFSRC_BASE + 0x20)
81 #define DVFSRC_EMI_REQUEST (DVFSRC_BASE + 0x24)
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_vcorefs.h61 #define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0)
62 #define DVFSRC_SW_REQ1 (DVFSRC_BASE + 0x4)
63 #define DVFSRC_SW_REQ2 (DVFSRC_BASE + 0x8)
64 #define DVFSRC_SW_REQ3 (DVFSRC_BASE + 0xC)
65 #define DVFSRC_SW_REQ4 (DVFSRC_BASE + 0x10)
66 #define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x14)
67 #define DVFSRC_SW_REQ6 (DVFSRC_BASE + 0x18)
68 #define DVFSRC_SW_REQ7 (DVFSRC_BASE + 0x1C)
69 #define DVFSRC_SW_REQ8 (DVFSRC_BASE + 0x20)
70 #define DVFSRC_EMI_REQUEST (DVFSRC_BASE + 0x24)
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_vcorefs.h50 #define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0)
51 #define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x14)
52 #define DVFSRC_INT_EN (DVFSRC_BASE + 0xC8)
53 #define DVFSRC_MD_TURBO (DVFSRC_BASE + 0xDC)
54 #define DVFSRC_PCIE_VCORE_REQ (DVFSRC_BASE + 0xE0)
55 #define DVFSRC_VCORE_USER_REQ (DVFSRC_BASE + 0xE4)
56 #define DVFSRC_TIMEOUT_NEXTREQ (DVFSRC_BASE + 0xF8)
57 #define DVFSRC_LEVEL_LABEL_0_1 (DVFSRC_BASE + 0x100)
58 #define DVFSRC_LEVEL_LABEL_2_3 (DVFSRC_BASE + 0x104)
59 #define DVFSRC_LEVEL_LABEL_4_5 (DVFSRC_BASE + 0x108)
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8192/include/
H A Dplatform_def.h44 #define DVFSRC_BASE (IO_PHYS + 0x00012000) macro
/rk3399_ARM-atf/plat/mediatek/mt8186/include/
H A Dplatform_def.h52 #define DVFSRC_BASE (IO_PHYS + 0x00012000) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/include/
H A Dplatform_def.h46 #define DVFSRC_BASE (IO_PHYS + 0x00012000) macro
/rk3399_ARM-atf/plat/mediatek/mt8189/include/
H A Dplatform_def.h51 #define DVFSRC_BASE (IO_PHYS + 0x0C00F000) macro
/rk3399_ARM-atf/plat/mediatek/mt8183/include/
H A Dplatform_def.h35 #define DVFSRC_BASE (IO_PHYS + 0x12000) macro