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Searched refs:CRU_PLL_CON (Results 1 – 11 of 11) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/soc/
H A Dsoc.c59 CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in set_pll_slow_mode()
68 CRU_PLL_CON(pll_id, 3), PLL_NOMAL_MODE); in set_pll_normal_mode()
78 CRU_PLL_CON(pll_id, 3), PLL_BYPASS_MODE); in set_pll_bypass()
126 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in restore_pll()
128 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK); in restore_pll()
129 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK); in restore_pll()
130 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]); in restore_pll()
131 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK); in restore_pll()
132 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK); in restore_pll()
135 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK); in restore_pll()
[all …]
H A Dsoc.h16 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) macro
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/
H A Dsuspend.c655 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in pmusram_restore_pll()
657 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK); in pmusram_restore_pll()
658 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK); in pmusram_restore_pll()
659 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]); in pmusram_restore_pll()
660 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK); in pmusram_restore_pll()
661 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK); in pmusram_restore_pll()
663 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK); in pmusram_restore_pll()
665 while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) & in pmusram_restore_pll()
710 dpll_data[i] = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, i)); in dmc_suspend()
H A Ddfs.c1716 refdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) & 0x3f; in ddr_get_rate()
1717 fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff; in ddr_get_rate()
1719 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 8) & 0x7; in ddr_get_rate()
1721 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 12) & 0x7; in ddr_get_rate()
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/
H A Drk3588_clk.c390 m = (mmio_read_32(DSUCRU_BASE + CRU_PLL_CON(16)) >> in rk3588_lpll_get_rate()
393 p = (mmio_read_32(DSUCRU_BASE + CRU_PLL_CON(17)) >> in rk3588_lpll_get_rate()
396 s = (mmio_read_32(DSUCRU_BASE + CRU_PLL_CON(17)) >> in rk3588_lpll_get_rate()
399 k = (mmio_read_32(DSUCRU_BASE + CRU_PLL_CON(18)) >> in rk3588_lpll_get_rate()
466 mmio_write_32(BIGCORE0CRU_BASE + CRU_PLL_CON(1), CRU_PLL_POWER_DOWN); in clk_scmi_b0pll_disable()
560 m = (mmio_read_32(BIGCORE0CRU_BASE + CRU_PLL_CON(0)) >> in rk3588_b0pll_get_rate()
563 p = (mmio_read_32(BIGCORE0CRU_BASE + CRU_PLL_CON(1)) >> in rk3588_b0pll_get_rate()
566 s = (mmio_read_32(BIGCORE0CRU_BASE + CRU_PLL_CON(1)) >> in rk3588_b0pll_get_rate()
569 k = (mmio_read_32(BIGCORE0CRU_BASE + CRU_PLL_CON(2)) >> in rk3588_b0pll_get_rate()
635 mmio_write_32(BIGCORE1CRU_BASE + CRU_PLL_CON(9), CRU_PLL_POWER_DOWN); in clk_scmi_b1pll_disable()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3576/scmi/
H A Drk3576_clk.c499 m = (mmio_read_32(CCI_CRU_BASE + CRU_PLL_CON(16)) >> in rk3576_lpll_get_rate()
502 p = (mmio_read_32(CCI_CRU_BASE + CRU_PLL_CON(17)) >> in rk3576_lpll_get_rate()
505 s = (mmio_read_32(CCI_CRU_BASE + CRU_PLL_CON(17)) >> in rk3576_lpll_get_rate()
508 k = (mmio_read_32(CCI_CRU_BASE + CRU_PLL_CON(18)) >> in rk3576_lpll_get_rate()
667 m = (mmio_read_32(CRU_BASE + CRU_PLL_CON(0)) >> in rk3576_bpll_get_rate()
670 p = (mmio_read_32(CRU_BASE + CRU_PLL_CON(1)) >> in rk3576_bpll_get_rate()
673 s = (mmio_read_32(CRU_BASE + CRU_PLL_CON(1)) >> in rk3576_bpll_get_rate()
676 k = (mmio_read_32(CRU_BASE + CRU_PLL_CON(2)) >> in rk3576_bpll_get_rate()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/
H A Dpmu.c586 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in clst_pwr_domain_suspend()
599 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in clst_pwr_domain_suspend()
619 pll_st = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 3)) >> in clst_pwr_domain_resume()
1297 (i >= CRU_PLL_CON(ABPLL_ID, 0) && in cru_register_restore()
1298 i <= CRU_PLL_CON(DPLL_ID, 5))) in cru_register_restore()
1301 if ((i == CRU_PLL_CON(ALPLL_ID, 2)) || in cru_register_restore()
1302 (i == CRU_PLL_CON(CPLL_ID, 2)) || in cru_register_restore()
1303 (i == CRU_PLL_CON(GPLL_ID, 2)) || in cru_register_restore()
1304 (i == CRU_PLL_CON(NPLL_ID, 2)) || in cru_register_restore()
1305 (i == CRU_PLL_CON(VPLL_ID, 2))) in cru_register_restore()
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/soc/
H A Dsoc.h43 #define CRU_PLL_CON(i) ((i) * 0x4) macro
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/soc/
H A Dsoc.h33 #define CRU_PLL_CON(i) ((i) * 0x4) macro
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/pmu/
H A Dpm_pd_regs.c166 if ((mmio_read_32(pll_base + CRU_PLL_CON(1)) & CRU_PLLCON1_PWRDOWN) != 0) in pm_pll_wait_lock()
170 if ((mmio_read_32(pll_base + CRU_PLL_CON(6)) & CRU_PLLCON6_LOCK_STATUS) != 0) in pm_pll_wait_lock()
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/
H A Dpmu.c1396 if ((mmio_read_32(pll_base + CRU_PLL_CON(1)) & CRU_PLLCON1_PWRDOWN) != 0) in pm_pll_wait_lock()
1400 if (mmio_read_32(pll_base + CRU_PLL_CON(6)) & in pm_pll_wait_lock()