Searched refs:CRU_GLB_RST_CON (Results 1 – 13 of 13) sorted by relevance
| /rk3399_ARM-atf/plat/rockchip/px30/drivers/soc/ |
| H A D | soc.c | 91 tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON); in soc_reset_config_all()
93 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp); in soc_reset_config_all()
109 tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON); in px30_soc_reset_config()
111 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp); in px30_soc_reset_config()
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| H A D | soc.h | 57 #define CRU_GLB_RST_CON 0xc0 macro
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| /rk3399_ARM-atf/plat/rockchip/rk3588/drivers/soc/ |
| H A D | soc.c | 70 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, 0xffdf); in system_reset_init()
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| H A D | soc.h | 52 #define CRU_GLB_RST_CON 0xc10 macro
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| /rk3399_ARM-atf/plat/rockchip/rk3576/drivers/soc/ |
| H A D | soc.c | 92 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, 0xffdf); in system_reset_init()
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| H A D | soc.h | 46 #define CRU_GLB_RST_CON 0xc10 macro
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| /rk3399_ARM-atf/plat/rockchip/rk3288/drivers/soc/ |
| H A D | soc.c | 211 temp_val = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON); in rockchip_soc_soft_reset()
214 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, temp_val); in rockchip_soc_soft_reset()
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| H A D | soc.h | 51 #define CRU_GLB_RST_CON 0x1f0 macro
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| /rk3399_ARM-atf/plat/rockchip/rk3368/drivers/soc/ |
| H A D | soc.c | 197 temp_val = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON) | in rockchip_soc_soft_reset()
200 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, temp_val); in rockchip_soc_soft_reset()
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| H A D | soc.h | 89 #define CRU_GLB_RST_CON 0x388 macro
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| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/soc/ |
| H A D | soc.h | 188 #define CRU_GLB_RST_CON 0x0510 macro
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| H A D | soc.c | 325 mmio_clrbits_32(CRU_BASE + CRU_GLB_RST_CON, in soc_global_soft_reset_init()
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| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/ |
| H A D | suspend.c | 486 mmio_clrsetbits_32(CRU_BASE + CRU_GLB_RST_CON, 0x3, 0x3); in dram_all_config()
673 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, 1 << 1); in pmusram_enable_watchdog()
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