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Searched refs:CPC_MCUSYS_PWR_ON_MASK (Results 1 – 13 of 13) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv3_2/
H A Dmt_cpu_pm_cpc.c54 mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, MCUSYS_PROT_CLR); in mtk_cpu_pm_mcusys_prot_release()
65 mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, CPUSYS_PROT_CLR); in mtk_cpu_pm_cluster_prot_release()
/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v2/
H A Dmcucfg.h26 #define CPC_MCUSYS_PWR_ON_MASK (MCUSYS_CPC_BASE + 0x128) macro
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/mcdi/
H A Dmt_cpu_pm_cpc.c56 mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, MCUSYS_PROT_CLR); in mtk_cpu_pm_mcusys_prot_release()
69 mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, CPUSYS_PROT_CLR); in mtk_cpu_pm_cluster_prot_release()
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/mcdi/
H A Dmt_cpu_pm_cpc.c56 mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, MCUSYS_PROT_CLR); in mtk_cpu_pm_mcusys_prot_release()
69 mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, CPUSYS_PROT_CLR); in mtk_cpu_pm_cluster_prot_release()
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/mcdi/
H A Dmt_cpu_pm_cpc.c56 mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, MCUSYS_PROT_CLR); in mtk_cpu_pm_mcusys_prot_release()
69 mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, CPUSYS_PROT_CLR); in mtk_cpu_pm_cluster_prot_release()
/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v3/
H A Dmcucfg.h26 #define CPC_MCUSYS_PWR_ON_MASK (MCUSYS_CPC_BASE + 0x128) macro
/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v4/
H A Dmcucfg.h26 #define CPC_MCUSYS_PWR_ON_MASK (MCUSYS_CPC_BASE + 0x128) macro
/rk3399_ARM-atf/plat/mediatek/drivers/mcusys/v1/
H A Dmcucfg.h45 #define CPC_MCUSYS_PWR_ON_MASK (MCUCFG_BASE + 0xA828) macro
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/
H A Dmt_cpu_pm_cpc.c83 mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, MCUSYS_PROT_CLR); in mtk_cpu_pm_mcusys_prot_release()
130 mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, CPUSYS_PROT_CLR); in mtk_cpu_pm_cluster_prot_release()
/rk3399_ARM-atf/plat/mediatek/mt8192/include/
H A Dmcucfg.h92 #define CPC_MCUSYS_PWR_ON_MASK MCUCFG_REG(0xa828) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/include/
H A Dmcucfg.h92 #define CPC_MCUSYS_PWR_ON_MASK MCUCFG_REG(0xa828) macro
/rk3399_ARM-atf/plat/mediatek/mt8186/include/
H A Dmcucfg.h92 #define CPC_MCUSYS_PWR_ON_MASK MCUCFG_REG(0xa828) macro
/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v1/
H A Dmcucfg.h90 #define CPC_MCUSYS_PWR_ON_MASK (MCUCFG_BASE + 0xa828) macro