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Searched refs:CPC_MCUSYS_CPC_DBG_SETTING (Results 1 – 13 of 13) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv3_2/
H A Dmt_cpu_pm_cpc.c153 mmio_setbits_32(CPC_MCUSYS_CPC_DBG_SETTING, CPC_PROF_EN); in mtk_cpc_config()
155 mmio_clrbits_32(CPC_MCUSYS_CPC_DBG_SETTING, CPC_PROF_EN); in mtk_cpc_config()
188 res = (mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING) & CPC_PROF_EN) ? 1 : 0; in mtk_cpc_read_config()
242 mmio_setbits_32(CPC_MCUSYS_CPC_DBG_SETTING, (CPC_DBG_EN | CPC_CALC_EN)); in mtk_cpc_init()
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/mcdi/
H A Dmt_cpu_pm_cpc.c169 reg = CPC_MCUSYS_CPC_DBG_SETTING; in mtk_cpc_config()
211 res = (mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING) & CPC_PROF_EN) ? in mtk_cpc_read_config()
255 mmio_write_32(CPC_MCUSYS_CPC_DBG_SETTING, in mtk_cpc_init()
256 mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING) in mtk_cpc_init()
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/mcdi/
H A Dmt_cpu_pm_cpc.c169 reg = CPC_MCUSYS_CPC_DBG_SETTING; in mtk_cpc_config()
211 res = (mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING) & CPC_PROF_EN) ? in mtk_cpc_read_config()
255 mmio_write_32(CPC_MCUSYS_CPC_DBG_SETTING, in mtk_cpc_init()
256 mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING) in mtk_cpc_init()
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/mcdi/
H A Dmt_cpu_pm_cpc.c169 reg = CPC_MCUSYS_CPC_DBG_SETTING; in mtk_cpc_config()
211 res = (mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING) & CPC_PROF_EN) ? in mtk_cpc_read_config()
255 mmio_write_32(CPC_MCUSYS_CPC_DBG_SETTING, in mtk_cpc_init()
256 mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING) in mtk_cpc_init()
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/
H A Dmt_cpu_pm_cpc.c241 mmio_setbits_32(CPC_MCUSYS_CPC_DBG_SETTING, CPC_FREEZE); in mtk_cpc_time_freeze()
243 mmio_clrbits_32(CPC_MCUSYS_CPC_DBG_SETTING, CPC_FREEZE); in mtk_cpc_time_freeze()
267 reg = CPC_MCUSYS_CPC_DBG_SETTING; in mtk_cpc_config()
291 res = mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING) & CPC_PROF_EN in mtk_cpc_read_config()
341 reg = CPC_MCUSYS_CPC_DBG_SETTING; in mtk_cpc_prof_enable()
691 mmio_setbits_32(CPC_MCUSYS_CPC_DBG_SETTING, in mtk_cpc_init()
/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v2/
H A Dmcucfg.h32 #define CPC_MCUSYS_CPC_DBG_SETTING (MCUSYS_CPC_BASE + 0x200) macro
/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v3/
H A Dmcucfg.h32 #define CPC_MCUSYS_CPC_DBG_SETTING (MCUSYS_CPC_BASE + 0x200) macro
/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v4/
H A Dmcucfg.h32 #define CPC_MCUSYS_CPC_DBG_SETTING (MCUSYS_CPC_BASE + 0x200) macro
/rk3399_ARM-atf/plat/mediatek/drivers/mcusys/v1/
H A Dmcucfg.h49 #define CPC_MCUSYS_CPC_DBG_SETTING (MCUCFG_BASE + 0xAB00) macro
/rk3399_ARM-atf/plat/mediatek/mt8192/include/
H A Dmcucfg.h95 #define CPC_MCUSYS_CPC_DBG_SETTING MCUCFG_REG(0xab00) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/include/
H A Dmcucfg.h95 #define CPC_MCUSYS_CPC_DBG_SETTING MCUCFG_REG(0xab00) macro
/rk3399_ARM-atf/plat/mediatek/mt8186/include/
H A Dmcucfg.h95 #define CPC_MCUSYS_CPC_DBG_SETTING MCUCFG_REG(0xab00) macro
/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v1/
H A Dmcucfg.h95 #define CPC_MCUSYS_CPC_DBG_SETTING (MCUCFG_BASE + 0xab00) macro