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Searched refs:CPC_MCUSYS_CLUSTER_COUNTER_CLR (Results 1 – 13 of 13) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv3_2/
H A Dmt_cpu_pm_cpc.c81 mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, 0x3); in mtk_cpc_cluster_cnt_backup()
172 mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, 0x3); in mtk_cpc_config()
/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v2/
H A Dmcucfg.h44 #define CPC_MCUSYS_CLUSTER_COUNTER_CLR (MCUSYS_CPC_BASE + 0x274) macro
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/mcdi/
H A Dmt_cpu_pm_cpc.c91 mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, clr_mask); in mtk_cpc_cluster_cnt_backup()
190 reg = CPC_MCUSYS_CLUSTER_COUNTER_CLR; in mtk_cpc_config()
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/mcdi/
H A Dmt_cpu_pm_cpc.c91 mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, clr_mask); in mtk_cpc_cluster_cnt_backup()
190 reg = CPC_MCUSYS_CLUSTER_COUNTER_CLR; in mtk_cpc_config()
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/mcdi/
H A Dmt_cpu_pm_cpc.c91 mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, clr_mask); in mtk_cpc_cluster_cnt_backup()
190 reg = CPC_MCUSYS_CLUSTER_COUNTER_CLR; in mtk_cpc_config()
/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v3/
H A Dmcucfg.h44 #define CPC_MCUSYS_CLUSTER_COUNTER_CLR (MCUSYS_CPC_BASE + 0x274) macro
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/
H A Dmt_cpu_pm_cpc.c157 mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, 0x3); in mtk_cpc_cluster_cnt_backup()
274 reg = CPC_MCUSYS_CLUSTER_COUNTER_CLR; in mtk_cpc_config()
491 mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, 0x3); in mtk_cpu_pm_counter_clear()
570 mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, 0x3); in mtk_cpu_pm_counter_update()
/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v4/
H A Dmcucfg.h46 #define CPC_MCUSYS_CLUSTER_COUNTER_CLR (MCUSYS_CPC_BASE + 0x294) macro
/rk3399_ARM-atf/plat/mediatek/drivers/mcusys/v1/
H A Dmcucfg.h57 #define CPC_MCUSYS_CLUSTER_COUNTER_CLR (MCUCFG_BASE + 0xAB74) macro
/rk3399_ARM-atf/plat/mediatek/mt8192/include/
H A Dmcucfg.h103 #define CPC_MCUSYS_CLUSTER_COUNTER_CLR MCUCFG_REG(0xab74) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/include/
H A Dmcucfg.h103 #define CPC_MCUSYS_CLUSTER_COUNTER_CLR MCUCFG_REG(0xab74) macro
/rk3399_ARM-atf/plat/mediatek/mt8186/include/
H A Dmcucfg.h103 #define CPC_MCUSYS_CLUSTER_COUNTER_CLR MCUCFG_REG(0xab74) macro
/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v1/
H A Dmcucfg.h107 #define CPC_MCUSYS_CLUSTER_COUNTER_CLR (MCUCFG_BASE + 0xab74) macro