| /rk3399_ARM-atf/plat/arm/board/fvp/ |
| H A D | fvp_drtm_addr.c | 28 } else if ((region_start >= ARM_DRAM2_BASE) && in plat_drtm_validate_ns_region()
29 (region_start < (ARM_DRAM2_BASE + ARM_DRAM2_SIZE)) && in plat_drtm_validate_ns_region()
30 (region_end >= ARM_DRAM2_BASE) && in plat_drtm_validate_ns_region()
31 (region_end < (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) { in plat_drtm_validate_ns_region()
|
| /rk3399_ARM-atf/plat/arm/board/morello/ |
| H A D | morello_bl2_setup.c | 44 ARM_DRAM2_BASE, ARM_DRAM2_BASE + dram2_size); in dmc_ecc_setup()
45 zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size); in dmc_ecc_setup()
46 flush_dcache_range(ARM_DRAM2_BASE, dram2_size); in dmc_ecc_setup()
86 ARM_DRAM2_BASE; in dmc_ecc_setup()
|
| /rk3399_ARM-atf/plat/nuvoton/common/ |
| H A D | nuvoton_pm.c | 38 if ((entrypoint >= ARM_DRAM2_BASE) && in arm_validate_ns_entrypoint()
39 (entrypoint < (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) { in arm_validate_ns_entrypoint()
|
| /rk3399_ARM-atf/plat/arm/board/juno/ |
| H A D | juno_ethosn_tzmp1_def.h | 19 #define JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE (ARM_DRAM2_BASE)
20 #define JUNO_ETHOSN_FW_TZC_PROT_DRAM2_END (ARM_DRAM2_BASE + \
|
| H A D | juno_security.c | 53 {ARM_DRAM2_BASE, ARM_DRAM2_END,
|
| /rk3399_ARM-atf/plat/arm/board/n1sdp/ |
| H A D | n1sdp_bl2_setup.c | 42 zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size); in dmc_ecc_setup()
43 flush_dcache_range(ARM_DRAM2_BASE, dram2_size); in dmc_ecc_setup()
|
| /rk3399_ARM-atf/plat/arm/common/ |
| H A D | arm_pm.c | 127 if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint < in arm_validate_ns_entrypoint()
128 (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) { in arm_validate_ns_entrypoint()
|
| H A D | arm_nor_psci_mem_protect.c | 29 {ARM_DRAM2_BASE, 1u << ONE_GB_SHIFT},
|
| /rk3399_ARM-atf/plat/arm/board/fvp_ve/include/ |
| H A D | platform_def.h | 29 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE macro
31 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \
101 ARM_DRAM2_BASE, \
|
| /rk3399_ARM-atf/plat/arm/board/automotive_rd/platform/rdaspen/include/ |
| H A D | platform_def.h | 97 #undef ARM_DRAM2_BASE
98 #define ARM_DRAM2_BASE ULL(0x20000000000) macro
206 #define RDASPEN_MAP_NS_DRAM2 MAP_REGION_FLAT(ARM_DRAM2_BASE, \
|
| /rk3399_ARM-atf/plat/arm/board/fvp/include/ |
| H A D | fvp_pas_def.h | 82 #define ARM_PAS_4_BASE ARM_DRAM2_BASE
|
| /rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/include/nrd2/ |
| H A D | nrd_ros_fw_def2.h | 80 {NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE, \
|
| /rk3399_ARM-atf/include/plat/nuvoton/common/ |
| H A D | npcm845x_arm_def.h | 203 #define ARM_DRAM2_BASE 0 /* PLAT_ARM_DRAM_BASE */ macro
205 #define ARM_DRAM2_END (ARM_DRAM2_BASE + ARM_DRAM2_SIZE - 1U)
272 ARM_DRAM2_BASE, ARM_DRAM2_SIZE, \
|
| /rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/include/nrd3/ |
| H A D | nrd_plat_arm_def3.h | 650 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE macro
652 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \
813 ARM_DRAM2_BASE, \
|
| /rk3399_ARM-atf/include/plat/arm/common/ |
| H A D | arm_def.h | 253 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE macro
255 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \
312 ARM_DRAM2_BASE, \
|
| H A D | plat_arm.h | 69 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
91 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
|
| /rk3399_ARM-atf/plat/arm/board/neoverse_rd/platform/rdv3/ |
| H A D | rdv3_common.c | 155 bank_ptr[1].base = ARM_DRAM2_BASE; in plat_rmmd_load_manifest()
|
| /rk3399_ARM-atf/plat/arm/board/corstone1000/common/include/ |
| H A D | platform_def.h | 102 #define ARM_DRAM2_BASE ARM_DRAM1_BASE macro
|