Merge "fix(arm): increase reserved DRAM1 mem for NS images" into integration

fix(arm): increase reserved DRAM1 mem for NS images

Defconfig kernels are now approaching 50MB, making the previous 64MB
allocation for both the kernel and initrd insufficient. To accommodate
this g

fix(arm): increase reserved DRAM1 mem for NS images

Defconfig kernels are now approaching 50MB, making the previous 64MB
allocation for both the kernel and initrd insufficient. To accommodate
this growth, increase the reserved NS memory to 128MB.

Change-Id: Ifffdda4623ec7930e4c830a6a222933807d09882
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "Coverity: remove unnecessary header file includes" into integration

Coverity: remove unnecessary header file includes

This patch removes unnecessary header file includes
discovered by Coverity HFA option.

Change-Id: I2827c37c1c24866c87db0e206e681900545925d4
Signed-

Coverity: remove unnecessary header file includes

This patch removes unnecessary header file includes
discovered by Coverity HFA option.

Change-Id: I2827c37c1c24866c87db0e206e681900545925d4
Signed-off-by: Zelalem <zelalem.aweke@arm.com>

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Merge "Switch AARCH32/AARCH64 to __aarch64__" into integration

Switch AARCH32/AARCH64 to __aarch64__

NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.

All common C compilers pre-define the same macros to signal which
architecture the cod

Switch AARCH32/AARCH64 to __aarch64__

NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.

All common C compilers pre-define the same macros to signal which
architecture the code is being compiled for: __arm__ for AArch32 (or
earlier versions) and __aarch64__ for AArch64. There's no need for TF-A
to define its own custom macros for this. In order to unify code with
the export headers (which use __aarch64__ to avoid another dependency),
let's deprecate the AARCH32 and AARCH64 macros and switch the code base
over to the pre-defined standard macro. (Since it is somewhat
unintuitive that __arm__ only means AArch32, let's standardize on only
using __aarch64__.)

Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200
Signed-off-by: Julius Werner <jwerner@chromium.org>

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Merge pull request #1803 from sandrine-bailleux-arm/sb/arm-bl33-fixes

Fixes related to BL33 image on Arm platforms

Arm platforms: Rename PLAT_ARM_NS_IMAGE_OFFSET

PLAT_ARM_NS_IMAGE_OFFSET is in fact not an offset relative to some base
address, it is an absolute address. Rename it to avoid any confusion.

Change-I

Arm platforms: Rename PLAT_ARM_NS_IMAGE_OFFSET

PLAT_ARM_NS_IMAGE_OFFSET is in fact not an offset relative to some base
address, it is an absolute address. Rename it to avoid any confusion.

Change-Id: I1f7f5e8553cb267786afe7e5f3cd4d665b610d3f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Merge pull request #1784 from antonio-nino-diaz-arm/an/includes-arm

plat/arm: Cleanup of includes and drivers

plat/arm: Sanitise includes

Use full include paths like it is done for common includes.

This cleanup was started in commit d40e0e08283a ("Sanitise includes
across codebase"), but it only cleaned co

plat/arm: Sanitise includes

Use full include paths like it is done for common includes.

This cleanup was started in commit d40e0e08283a ("Sanitise includes
across codebase"), but it only cleaned common files and drivers. This
patch does the same to Arm platforms.

Change-Id: If982e6450bbe84dceb56d464e282bcf5d6d9ab9b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1726 from antonio-nino-diaz-arm/an/includes

Sanitise includes across codebase

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- inclu

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a282 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca33988b9 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1606 from satheesbalya-arm/sb1_2603_misra_plat

plat/arm: Fix misra warnings in platform code

plat/arm: Fix misra warnings in platform code

Change-Id: Ica944acc474a099219d50b041cfaeabd4f3d362f
Signed-off-by: Sathees Balya <sathees.balya@arm.com>

Merge pull request #1619 from antonio-nino-diaz-arm/an/norflash

plat/arm: Move norflash driver to drivers/ folder

plat/arm: Move norflash driver to drivers/ folder

This way it can be reused by other platforms if needed.

Note that this driver is designed to work with the Versatile Express NOR
flash of Juno and

plat/arm: Move norflash driver to drivers/ folder

This way it can be reused by other platforms if needed.

Note that this driver is designed to work with the Versatile Express NOR
flash of Juno and FVP. In said platforms, the memory is organized as an
interleaved memory of two chips with a 16 bit word.

Any platform that wishes to reuse it with a different configuration will
need to modify the driver so that it is more generic.

Change-Id: Ic721758425864e0cf42b7b9b04bf0d9513b6022e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1486 from antonio-nino-diaz-arm/an/psci-misra

Fix several MISRA defects in PSCI library

PSCI: Fix MISRA defects in platform code

Fix violations of MISRA C-2012 Rules 10.1, 10.3, 13.3, 14.4, 17.7 and
17.8.

Change-Id: I6c9725e428b5752f1d80684ec29cb6c52a5c0c2d
Signed-off-by: Antonio Nino

PSCI: Fix MISRA defects in platform code

Fix violations of MISRA C-2012 Rules 10.1, 10.3, 13.3, 14.4, 17.7 and
17.8.

Change-Id: I6c9725e428b5752f1d80684ec29cb6c52a5c0c2d
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1354 from robertovargas-arm/mem_protect

ARM platforms: Demonstrate mem_protect from el3_runtime

ARM platforms: Demonstrate mem_protect from el3_runtime

Previously mem_protect used to be only supported from BL2. This is not
helpful in the case when ARM TF-A BL2 is not used. This patch demonstra

ARM platforms: Demonstrate mem_protect from el3_runtime

Previously mem_protect used to be only supported from BL2. This is not
helpful in the case when ARM TF-A BL2 is not used. This patch demonstrates
mem_protect from el3_runtime firmware on ARM Platforms specifically
when RESET_TO_BL31 or RESET_TO_SP_MIN flag is set as BL2 may be absent
in these cases. The Non secure DRAM is dynamically mapped into EL3 mmap
tables temporarily and then the protected regions are then cleared. This
avoids the need to map the non secure DRAM permanently to BL31/sp_min.

The stack size is also increased, because DYNAMIC_XLAT_TABLES require
a bigger stack.

Change-Id: Ia44c594192ed5c5adc596c0cff2c7cc18c001fde
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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Merge pull request #1282 from robertovargas-arm/misra-changes

Misra changes

Fix MISRA rule 8.4 Part 1

Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined

Fixed for:
make DEBUG=1 PLAT=fvp LOG_LEVEL=50 al

Fix MISRA rule 8.4 Part 1

Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined

Fixed for:
make DEBUG=1 PLAT=fvp LOG_LEVEL=50 all

Change-Id: I7c2ad3f5c015411c202605851240d5347e4cc8c7
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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Merge pull request #1109 from robertovargas-arm/mem_protect

Mem protect

mem_protect: Add DRAM2 to the list of mem protected ranges

On ARM platforms, the maximum size of the address space is limited
to 32-bits as defined in arm_def.h. In order to access DRAM2, which
is d

mem_protect: Add DRAM2 to the list of mem protected ranges

On ARM platforms, the maximum size of the address space is limited
to 32-bits as defined in arm_def.h. In order to access DRAM2, which
is defined beyond the 32-bit address space, the maximum address space
is increased to 36-bits in AArch64. It is possible to increase the
virtual space for AArch32, but it is more difficult and not supported
for now.

NOTE - the actual maximum memory address space is platform dependent
and is checked at run-time by querying the PARange field in the
ID_AA64MMFR0_EL1 register.

Change-Id: I6cb05c78a63b1fed96db9a9773faca04a5b93d67
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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mem_protect: Add mem_protect support in Juno and FVP for DRAM1

mem_protect needs some kind of non-volatile memory because it has
to remember its state across reset and power down events.
The most su

mem_protect: Add mem_protect support in Juno and FVP for DRAM1

mem_protect needs some kind of non-volatile memory because it has
to remember its state across reset and power down events.
The most suitable electronic part for this feature is a NVRAM
which should be only accesible from the secure world. Juno and
FVP lack such hardware and for this reason the MEM_PROTECT
functionality is implemented with Flash EEPROM memory on both
boards, even though this memory is accesible from the non-secure
world. This is done only to show a full implementation of
these PSCI features, but an actual system shouldn't use a
non-secure NVRAM to implement it.

The EL3 runtime software will write the mem_protect flag and BL2
will read and clear the memory ranges if enabled. It is done in
BL2 because it reduces the time that TF needs access to the full
non-secure memory.

The memory layout of both boards is defined using macros which
take different values in Juno and FVP platforms. Generic platform
helpers are added that use the platform specific macros to generate
a mem_region_t that is valid for the platform.

Change-Id: I2c6818ac091a2966fa07a52c5ddf8f6fde4941e9
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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