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/optee_os/core/arch/arm/kernel/
H A Dentry_a64.S35 adr_l x1, stack_tmp_stride
36 ldr w1, [x1]
37 mul x1, x0, x1
45 add sp, x1, x0
76 read_feat_mte x1
144 ldp x0, x1, [sp, #THREAD_CORE_LOCAL_KEYS]
147 write_apiakeylo x1
171 mov x20, x1
198 adr x1, __data_end /* src */
201 ldr w4, [x1, x2] /* length of hashes etc */
[all …]
H A Dthread_a64.S71 mov sp, x1
74 ldr x1, [x0, THREAD_CTX_REGS_TPIDR_EL0]
75 msr tpidr_el0, x1
79 write_apiakeyhi x1
171 msr sp_el0, x1
178 write_apiakeyhi x1
232 msr tpidrro_el0, x1
244 ldr x1, [sp, #THREAD_CORE_LOCAL_KCODE_OFFSET]
245 add x0, x0, x1
252 mrs x1, vbar_el1
[all …]
H A Dmisc_a64.S21 mov x1, #MPIDR_VCPU_MASK
22 and x0, x0, x1
42 ubfx x1, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
43 add x0, x0, x1, LSL #(CFG_CORE_CLUSTER_SHIFT)
50 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
52 add x1, x1, x2, LSL #(CFG_CORE_CLUSTER_SHIFT)
53 add x0, x0, x1, LSL #(CFG_CORE_THREAD_SHIFT)
H A Darch_scall_a64.S17 uint64_t x1;
35 stp x0, x1, [sp, #SC_REC_X0]
57 sub x1, x6, #0x4
58 lsl x1, x1, #3
62 cmp x1, x0
63 csel x0, x1, x0, ge
74 mov x1, x5
115 ldr w3, [x1], #4
176 mov x1, #0 /* panic = false */
191 mov x1, #1 /* panic = true */
H A Dcache_helpers_a64.S30 add x1, x0, x1
36 cmp x0, x1
110 lsr x1, x0, x2 // extract cache type bits from clidr
111 and x1, x1, #7 // mask the bits for current cache only
112 cmp x1, #2 // see what cache we have at this level
117 mrs x1, ccsidr_el1 // read the new ccsidr
118 and x2, x1, #7 // extract the length of the cache lines
120 ubfx x4, x1, #3, #10 // maximum way number
228 add x1, x0, x1
234 cmp x0, x1
H A Dthread_optee_smc_a64.S82 mov x1, x0
92 mov x1, x0
102 mov x1, x0
112 mov x1, x0
122 mov x1, x0
132 mov x1, x0
185 push x1, x30
193 read_apiakeyhi x1
199 pop x1, xzr /* Match "push x1, x30" above */
216 mov x1, x21
H A Dspin_lock_a64.S76 mov x1, x0
78 .loop: ldaxr w0, [x1]
80 stxr w0, w2, [x1]
H A Darch_scall.c77 .x1 = pushed[2], in save_panic_regs_a32_ta()
126 (uaddr_t)regs->x1, in scall_save_panic_stack()
132 (uaddr_t)regs->x1); in scall_save_panic_stack()
141 save_panic_regs_a32_ta(tsd, (uint32_t *)regs->x1); in scall_save_panic_stack()
143 save_panic_regs_a64_ta(tsd, (uint64_t *)regs->x1); in scall_save_panic_stack()
H A Dthread_spmc_a64.S33 mov x1, #FFA_TARGET_INFO_MBZ /* Target info MBZ */
112 mov x1, #0 /* Pass NULL pointer for caller_sp, coming from NW */
142 push x1, x30
150 read_apiakeyhi x1
156 pop x1, xzr /* Match "push x1, x30" above */
/optee_os/core/arch/arm/plat-d06/
H A Dcore_pos_a64.S22 lsr x1, x0, 8
23 and x2, x1, 0x7
25 lsr x1, x0, 16
26 and x3, x1, 0x7
28 lsr x1, x0, 20
29 and x4, x1, 0x7
/optee_os/core/arch/arm/plat-rcar/
H A Dcore_pos_a64.S32 ubfx x1, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
68 lsl x1, x1, #1
69 2: lsl x1, x1, #1
70 add x0, x0, x1
/optee_os/core/arch/arm/plat-marvell/otx2/
H A Dcore_pos.S10 ubfx x1, x0, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
12 mul x1, x1, x2
14 add x0, x1, x2
/optee_os/core/arch/arm/plat-automotive_rd/
H A Drd1ae_core_pos.S20 ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
28 madd x1, x2, x4, x1
30 madd x0, x1, x4, x0
/optee_os/lib/libutils/ext/arch/arm/
H A Dmcount_a64.S47 adjust_pc x1, x30
52 get_lr_addr x1
63 stp x0, x1, [sp]
73 ldp x0, x1, [sp]
/optee_os/core/lib/libtomcrypt/src/ciphers/
H A Didea.c104 ushort16 x0, x1, x2, x3, t0, t1; in s_process_block() local
107 LOAD16(x1, in + 2); in s_process_block()
113 x1 += m_key[i*6+1]; in s_process_block()
118 t1 = t0 + (x1^x3); in s_process_block()
123 t0 ^= x1; in s_process_block()
124 x1 = x2^t1; in s_process_block()
130 x1 += m_key[LTC_IDEA_ROUNDS*6+2]; in s_process_block()
135 STORE16(x1, out + 4); in s_process_block()
/optee_os/core/arch/arm/plat-marvell/cn10k/
H A Dcore_pos.S12 mov_imm x1, MPIDR_AFFLVL_MASK
13 and x0, x1, x0, LSR #MPIDR_AFF2_SHIFT
/optee_os/lib/libutee/arch/arm/
H A Dutee_syscalls_a64.S21 stp x0, x1, [sp, #16]
27 ldp x0, x1, [sp, #16]
42 mov x1, sp
/optee_os/lib/libutils/isoc/arch/arm/
H A Dsetjmp_a64.S78 stp x0, x1, [sp, #-16]!
84 ldp x0, x1, [sp], #16
88 stp x0, x1, [sp, #-16]!
91 ldp x0, x1, [sp], #16
/optee_os/core/arch/arm/plat-vexpress/
H A Djuno_core_pos_a64.S12 and x1, x0, #MPIDR_CPU_MASK
15 add x0, x1, x0, LSR #6
/optee_os/core/lib/libtomcrypt/src/stream/sosemanuk/
H A Dsosemanuk.c175 #define SERPENT_LT(x0, x1, x2, x3) do { \ argument
178 x1 = x1 ^ x0 ^ x2; \
180 x1 = ROLc(x1, 1); \
182 x0 = x0 ^ x1 ^ x3; \
183 x2 = x2 ^ x3 ^ T32(x1 << 7); \
337 #define KA(zc, x0, x1, x2, x3) do { \ in sosemanuk_setiv() argument
339 x1 ^= st->kc[(zc) + 1]; \ in sosemanuk_setiv()
608 #define FSM(x0, x1, x2, x3, x4, x5, x6, x7, x8, x9) do { \ in s_sosemanuk_internal() argument
610 tt = XMUX(r1, s ## x1, s ## x8); \ in s_sosemanuk_internal()
621 #define LRU(x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, dd) do { \ in s_sosemanuk_internal() argument
[all …]
/optee_os/core/arch/arm/crypto/
H A Daes_modes_armv8a_ce_a64.S231 ld1 {v0.16b}, [x1]
252 ld1 {v0.16b-v1.16b}, [x1], #32 /* get 2 pt blocks */
256 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
266 ld1 {v0.16b}, [x1], #16 /* get next pt block */
291 ld1 {v0.16b-v1.16b}, [x1], #32 /* get 2 ct blocks */
295 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 ct blocks */
305 ld1 {v0.16b}, [x1], #16 /* get next ct block */
327 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
343 ld1 {v0.16b}, [x1], #16 /* get next pt block */
369 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 ct blocks */
[all …]
H A Dsm4_armv8a_ce_a64.S378 ld1 {RK0.4s}, [x1]
405 ld1 {RK7.4s}, [x1]
460 ld1 {BLK0.16b, BLK1.16b, BLK2.16b, BLK3.16b}, [x1], #64
461 ld1 {BLK4.16b, BLK5.16b, BLK6.16b, BLK7.16b}, [x1], #64
477 ld1 {BLK0.16b, BLK1.16b, BLK2.16b, BLK3.16b}, [x1], #64
484 ld1 {BLK0.16b, BLK1.16b, BLK2.16b}, [x1], #48
491 ld1 {BLK0.16b, BLK1.16b}, [x1], #32
498 ld1 {BLK0.16b}, [x1], #16
529 ld1 {BLK0.16b, BLK1.16b, BLK2.16b, BLK3.16b}, [x1], #64
554 ld1 {BLK0.16b}, [x1], #16
[all …]
H A Dsha3_armv8a_ce_a64.S61 ld1 {v25.8b-v28.8b}, [x1], #32
62 ld1 {v29.8b-v31.8b}, [x1], #24
75 ld1 {v25.8b-v28.8b}, [x1], #32
76 ld1 {v29.8b-v30.8b}, [x1], #16
88 ld1 {v25.8b-v28.8b}, [x1], #32
99 ld1 {v25.8b-v28.8b}, [x1], #32
109 ld1 {v25.8b-v28.8b}, [x1], #32
117 2: ld1 {v29.8b}, [x1], #8
122 3: ld1 {v25.8b-v26.8b}, [x1], #16
H A Dsm4_armv8a_aese_a64.S475 ld1 {v5.4s}, [x1]
550 ld1 {BLK0.16b, BLK1.16b, BLK2.16b, BLK3.16b}, [x1], #64
551 ld1 {BLK4.16b, BLK5.16b, BLK6.16b, BLK7.16b}, [x1], #64
567 ld1 {BLK0.16b, BLK1.16b, BLK2.16b, BLK3.16b}, [x1], #64
574 ld1 {BLK0.16b, BLK1.16b, BLK2.16b}, [x1], #48
581 ld1 {BLK0.16b, BLK1.16b}, [x1], #32
588 ld1 {BLK0.16b}, [x1], #16
620 ld1 {BLK0.16b, BLK1.16b, BLK2.16b, BLK3.16b}, [x1], #64
645 ld1 {BLK0.16b}, [x1], #16
681 ld1 {BLK0.16b, BLK1.16b, BLK2.16b, BLK3.16b}, [x1], #64
[all …]
/optee_os/core/arch/arm/dts/
H A Dstm32mp151.dtsi404 reg = <0x0 0x1>;
407 reg = <0x4 0x1>;
626 dmas = <&dmamux1 18 0x400 0x1>,
627 <&dmamux1 19 0x400 0x1>,
628 <&dmamux1 20 0x400 0x1>,
629 <&dmamux1 21 0x400 0x1>,
630 <&dmamux1 22 0x400 0x1>;
660 dmas = <&dmamux1 23 0x400 0x1>,
661 <&dmamux1 24 0x400 0x1>,
662 <&dmamux1 25 0x400 0x1>,
[all …]

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