| /optee_os/core/include/dt-bindings/clock/ |
| H A D | stm32mp25-clksrc.h | 48 #define CLK_CFG(clk_id, sel, div, state) ((CMD_CLK << CMD_SHIFT) |\ argument
52 ((sel) << CLK_SEL_SHIFT))
74 #define MUX_CFG(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ argument
76 (sel)))
197 #define FLEXGEN_CFG(ch, sel, pdiv, fdiv) ((CMD_FLEXGEN << CMD_SHIFT) |\ argument
199 ((sel) << FLEX_SEL_SHIFT) |\
211 #define MCO_CFG(addr, sel, status) (CMD_ADDR_BIT |\ argument
214 (sel))
229 #define OBS_CFG(id, status, int_ext, div, inv, sel)\ argument
236 ((sel) << OBS_SEL_SHIFT))
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| H A D | stm32mp21-clksrc.h | 47 #define MUX_CFG(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ argument
49 (sel)))
150 #define FLEXGEN_CFG(ch, sel, pdiv, fdiv) ((CMD_FLEXGEN << CMD_SHIFT) |\ argument
152 ((sel) << FLEX_SEL_SHIFT) |\
164 #define MCO_CFG(addr, sel, status) (CMD_ADDR_BIT |\ argument
167 (sel))
182 #define OBS_CFG(id, status, int_ext, div, inv, sel)\ argument
189 ((sel) << OBS_SEL_SHIFT))
212 #define OBS_INT_CFG(id, status, div, inv, sel)\ argument
213 OBS_CFG((id), (status), OBS_INT, (div), (inv), (sel))
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| H A D | stm32mp13-clksrc.h | 71 #define CLKSRC(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ argument
73 (sel))
76 #define CLK_SRC(clk_id, sel) ((CMD_CLK << CMD_SHIFT) |\ argument
78 (sel) | CLK_ON_MASK)
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| /optee_os/core/drivers/clk/ |
| H A D | clk-stm32mp15.c | 202 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ member
239 .sel = (_parent_sel), \
251 .sel = _UNKNOWN_SEL, \
263 .sel = (_parent_sel), \
275 .sel = _UNKNOWN_SEL, \
290 .sel = (_parent_sel), \
300 .sel = _UNKNOWN_SEL, \
616 return (enum stm32mp1_parent_sel)gate_ref(i)->sel; in stm32mp1_clk_get_sel()
626 const struct stm32mp1_clk_sel *sel = NULL; in stm32mp1_clk_get_parent() local
652 sel = clk_sel_ref(s); in stm32mp1_clk_get_parent()
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| H A D | clk-stm32mp13.c | 937 int sel = (data & CLK_SEL_MASK) >> CLK_SEL_SHIFT; in stm32_clk_configure_clk() local
964 if (stm32_mux_set_parent(mux, sel)) in stm32_clk_configure_clk()
976 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT; in stm32_clk_configure_mux() local
982 if (sel == 0) in stm32_clk_configure_mux()
989 if (stm32_mux_set_parent(mux, sel)) in stm32_clk_configure_mux()
1071 static unsigned long clk_stm32_pll_get_oscillator_rate(int sel) in clk_stm32_pll_get_oscillator_rate() argument
1075 assert(sel >= 0 && sel < (int)ARRAY_SIZE(osc)); in clk_stm32_pll_get_oscillator_rate()
1077 return clk_stm32_get_rate_oscillateur(osc[sel]); in clk_stm32_pll_get_oscillator_rate()
1084 int sel = (vco->src & MUX_SEL_MASK) >> MUX_SEL_SHIFT; in clk_stm32_pll_compute_cfgr1() local
1089 refclk = clk_stm32_pll_get_oscillator_rate(sel) / (divm + 1U); in clk_stm32_pll_compute_cfgr1()
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| H A D | clk-stm32mp21.c | 774 static unsigned long clk_stm32_pll_get_oscillator_rate(unsigned int sel) in clk_stm32_pll_get_oscillator_rate() argument
778 assert(sel < ARRAY_SIZE(osc)); in clk_stm32_pll_get_oscillator_rate()
780 return clk_stm32_get_rate_oscillator(osc[sel]); in clk_stm32_pll_get_oscillator_rate()
1419 int sel = (pllsrc & MUX_SEL_MASK) >> MUX_SEL_SHIFT; in clk_stm32_pll_config_output() local
1420 unsigned long refclk = clk_stm32_pll_get_oscillator_rate(sel); in clk_stm32_pll_config_output()
1518 int sel = (src & MUX_SEL_MASK) >> MUX_SEL_SHIFT; in clk_stm32_pll_set_mux() local
1520 if (stm32_mux_set_parent(mux, sel)) in clk_stm32_pll_set_mux()
1530 int sel = (src & MUX_SEL_MASK) >> MUX_SEL_SHIFT; in clk_stm32_pll_check_mux() local
1532 return stm32_mux_get_parent(mux) != (size_t)sel ? 1 : 0; in clk_stm32_pll_check_mux()
1539 int sel = (pll_conf->src & MUX_SEL_MASK) >> MUX_SEL_SHIFT; in clk_stm32_pll1_init() local
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| H A D | clk-stm32mp25.c | 782 static unsigned long clk_stm32_pll_get_oscillator_rate(unsigned int sel) in clk_stm32_pll_get_oscillator_rate() argument
786 assert(sel < ARRAY_SIZE(osc)); in clk_stm32_pll_get_oscillator_rate()
788 return clk_stm32_get_rate_oscillator(osc[sel]); in clk_stm32_pll_get_oscillator_rate()
1437 int sel = (pllsrc & MUX_SEL_MASK) >> MUX_SEL_SHIFT; in clk_stm32_pll_config_output() local
1438 unsigned long refclk = clk_stm32_pll_get_oscillator_rate(sel); in clk_stm32_pll_config_output()
1536 int sel = (src & MUX_SEL_MASK) >> MUX_SEL_SHIFT; in clk_stm32_pll_set_mux() local
1538 if (stm32_mux_set_parent(mux, sel)) in clk_stm32_pll_set_mux()
1549 int sel = (pll_conf->src & MUX_SEL_MASK) >> MUX_SEL_SHIFT; in clk_stm32_pll1_init() local
1557 refclk = clk_stm32_pll_get_oscillator_rate(sel); in clk_stm32_pll1_init()
1825 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT; in stm32_clk_configure_mux() local
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| H A D | clk-stm32-core.h | 131 TEE_Result stm32_mux_set_parent(uint16_t pid, uint8_t sel);
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| H A D | clk-stm32-core.c | 49 TEE_Result stm32_mux_set_parent(uint16_t mux_id, uint8_t sel) in stm32_mux_set_parent() argument
56 io_clrsetbits32(address, mask, (sel << mux->shift) & mask); in stm32_mux_set_parent()
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