| /optee_os/core/drivers/clk/sam/ |
| H A D | at91_programmable.c | 18 #define PROG_PRES(layout, pckr) \ argument
20 typeof(layout) __layout = layout; \
29 const struct clk_programmable_layout *layout; member
36 const struct clk_programmable_layout *layout = prog->layout; in clk_programmable_get_rate() local
40 if (layout->is_pres_direct) in clk_programmable_get_rate()
41 rate = parent_rate / (PROG_PRES(layout, pckr) + 1); in clk_programmable_get_rate()
43 rate = parent_rate >> PROG_PRES(layout, pckr); in clk_programmable_get_rate()
51 const struct clk_programmable_layout *layout = prog->layout; in clk_programmable_set_parent() local
52 unsigned int mask = layout->css_mask; in clk_programmable_set_parent()
55 if (layout->have_slck_mck) in clk_programmable_set_parent()
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| H A D | at91_peripheral.c | 26 const struct clk_pcr_layout *layout; member
63 io_write32(periph->base + periph->layout->offset, in clk_sam9x5_peripheral_enable()
64 (periph->id & periph->layout->pid_mask)); in clk_sam9x5_peripheral_enable()
65 io_clrsetbits32(periph->base + periph->layout->offset, in clk_sam9x5_peripheral_enable()
66 periph->layout->div_mask | periph->layout->cmd | in clk_sam9x5_peripheral_enable()
68 field_prep(periph->layout->div_mask, periph->div) | in clk_sam9x5_peripheral_enable()
69 periph->layout->cmd | in clk_sam9x5_peripheral_enable()
82 io_write32(periph->base + periph->layout->offset, in clk_sam9x5_peripheral_disable()
83 (periph->id & periph->layout->pid_mask)); in clk_sam9x5_peripheral_disable()
84 io_clrsetbits32(periph->base + periph->layout->offset, in clk_sam9x5_peripheral_disable()
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| H A D | at91_generated.c | 26 const struct clk_pcr_layout *layout; member
35 io_write32(gck->base + gck->layout->offset, in clk_generated_enable()
36 (gck->id & gck->layout->pid_mask)); in clk_generated_enable()
37 io_clrsetbits32(gck->base + gck->layout->offset, in clk_generated_enable()
38 AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask | in clk_generated_enable()
39 gck->layout->cmd | AT91_PMC_PCR_GCKEN, in clk_generated_enable()
40 field_prep(gck->layout->gckcss_mask, gck->parent_id) | in clk_generated_enable()
41 gck->layout->cmd | in clk_generated_enable()
53 io_write32(gck->base + gck->layout->offset, in clk_generated_disable()
54 gck->id & gck->layout->pid_mask); in clk_generated_disable()
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| H A D | at91_pll.c | 21 #define PLL_MUL(reg, layout) \ argument
23 typeof(layout) __layout = layout; \
28 #define PLL_MUL_MASK(layout) ((layout)->mul_mask) argument
29 #define PLL_MUL_MAX(layout) (PLL_MUL_MASK(layout) + 1) argument
43 const struct clk_pll_layout *layout; member
57 const struct clk_pll_layout *layout = pll->layout; in clk_pll_enable() local
70 mul = PLL_MUL(pllr, layout); in clk_pll_enable()
85 io_clrsetbits32(pll->base + offset, layout->pllr_mask, in clk_pll_enable()
88 ((pll->mul & layout->mul_mask) << layout->mul_shift)); in clk_pll_enable()
99 unsigned int mask = pll->layout->pllr_mask; in clk_pll_disable()
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| H A D | clk-sam9x60-pll.c | 25 #define PLL_MUL(reg, layout) \ argument
27 typeof(layout) __layout = layout; \
32 #define PLL_MUL_MASK(layout) ((layout)->mul_mask) argument
33 #define PLL_MUL_MAX(layout) (PLL_MUL_MASK(layout) + 1) argument
43 const struct clk_pll_layout *layout; member
106 cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift; in sam9x60_frac_pll_set()
107 cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift; in sam9x60_frac_pll_set()
121 SHIFT_U32(frac->mul, core->layout->mul_shift) | in sam9x60_frac_pll_set()
122 SHIFT_U32(frac->frac, core->layout->frac_shift)); in sam9x60_frac_pll_set()
242 SHIFT_U32(frac->mul, core->layout->mul_shift) | in sam9x60_frac_pll_set_rate_chg()
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| H A D | at91_master.c | 22 const struct clk_master_layout *layout; member
56 const struct clk_master_layout *layout = master->layout; in clk_master_div_get_rate() local
59 mckr = io_read32(master->base + master->layout->offset); in clk_master_div_get_rate()
61 mckr &= layout->mask; in clk_master_div_get_rate()
88 val = io_read32(master->base + master->layout->offset); in clk_master_pres_get_rate()
90 pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; in clk_master_pres_get_rate()
102 mckr = io_read32(master->base + master->layout->offset); in clk_master_pres_get_parent()
117 const struct clk_master_layout *layout, in at91_clk_register_master_internal() argument
137 master->layout = layout; in at91_clk_register_master_internal()
158 const struct clk_master_layout *layout, in at91_clk_register_master_pres() argument
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| H A D | at91_clk.h | 154 const struct clk_pll_layout *layout,
166 const struct clk_pll_layout *layout,
174 const struct clk_pll_layout *layout,
196 const struct clk_master_layout *layout,
203 const struct clk_master_layout *layout,
232 const struct clk_programmable_layout *layout);
240 const struct clk_pcr_layout *layout,
246 const struct clk_pcr_layout *layout,
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| H A D | sama7g5_clk.c | 96 const struct clk_pll_layout *layout; member
111 .layout = &pll_layout_frac,
123 .layout = &pll_layout_divpmc,
141 .layout = &pll_layout_frac,
154 .layout = &pll_layout_divpmc,
170 .layout = &pll_layout_frac,
182 .layout = &pll_layout_divpmc,
195 .layout = &pll_layout_frac,
203 .layout = &pll_layout_divpmc,
215 .layout = &pll_layout_frac,
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