25 #define PLL_MUL(reg, layout) \  argument
27 		typeof(layout) __layout = layout; \
32 #define PLL_MUL_MASK(layout)	((layout)->mul_mask)  argument
33 #define PLL_MUL_MAX(layout)	(PLL_MUL_MASK(layout) + 1)  argument
43 	const struct clk_pll_layout *layout;  member
106 	cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;  in sam9x60_frac_pll_set()
107 	cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;  in sam9x60_frac_pll_set()
121 		   SHIFT_U32(frac->mul, core->layout->mul_shift) |  in sam9x60_frac_pll_set()
122 		   SHIFT_U32(frac->frac, core->layout->frac_shift));  in sam9x60_frac_pll_set()
242 			   SHIFT_U32(frac->mul, core->layout->mul_shift) |  in sam9x60_frac_pll_set_rate_chg()
243 			   SHIFT_U32(frac->frac, core->layout->frac_shift));  in sam9x60_frac_pll_set_rate_chg()
280 	uint32_t enable_mask = enable ? core->layout->endiv_mask : 0;  in sam9x60_div_pll_set_div()
281 	uint32_t ena_val = enable ? BIT(core->layout->endiv_shift) : 0;  in sam9x60_div_pll_set_div()
287 			core->layout->div_mask | enable_mask,  in sam9x60_div_pll_set_div()
288 			SHIFT_U32(div, core->layout->div_shift) | ena_val);  in sam9x60_div_pll_set_div()
312 	cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;  in sam9x60_div_pll_set()
315 	if ((val & core->layout->endiv_mask) && cdiv == div->div)  in sam9x60_div_pll_set()
337 	io_clrbits32(regmap + AT91_PMC_PLL_CTRL0, core->layout->endiv_mask);  in sam9x60_div_pll_unprepare()
385 	cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;  in sam9x60_div_pll_set_rate_chg()
413 					  const struct clk_pll_layout *layout,  in sam9x60_clk_register_frac_pll()  argument
436 	frac->core.layout = layout;  in sam9x60_clk_register_frac_pll()
487 					 const struct clk_pll_layout *layout,  in sam9x60_clk_register_div_pll()  argument
515 	div->core.layout = layout;  in sam9x60_clk_register_div_pll()