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Searched refs:div_id (Results 1 – 9 of 9) sorted by relevance

/optee_os/core/drivers/clk/
H A Dclk-stm32-core.c287 uint32_t stm32_div_get_value(int div_id) in stm32_div_get_value() argument
290 const struct div_cfg *divider = &priv->div[div_id]; in stm32_div_get_value()
299 TEE_Result stm32_div_set_value(uint32_t div_id, uint32_t value) in stm32_div_set_value() argument
306 if (div_id >= priv->nb_div) in stm32_div_set_value()
309 divider = &priv->div[div_id]; in stm32_div_set_value()
321 static unsigned long stm32_div_get_rate(int div_id, unsigned long prate) in stm32_div_get_rate() argument
324 const struct div_cfg *divider = &priv->div[div_id]; in stm32_div_get_rate()
325 uint32_t val = stm32_div_get_value(div_id); in stm32_div_get_rate()
335 TEE_Result stm32_div_set_rate(int div_id, unsigned long rate, in stm32_div_set_rate() argument
339 const struct div_cfg *divider = &priv->div[div_id]; in stm32_div_set_rate()
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H A Dclk-stm32-core.h76 int div_id; member
81 int div_id; member
133 TEE_Result stm32_div_set_rate(int div_id, unsigned long rate,
136 uint32_t stm32_div_get_value(int div_id);
137 TEE_Result stm32_div_set_value(uint32_t div_id, uint32_t value);
210 .div_id = (_div_id),\
248 .div_id = (_div_id),\
H A Dclk-stm32mp13.c999 int div_id = (data & DIV_ID_MASK) >> DIV_ID_SHIFT; in stm32_clk_configure_div() local
1002 return stm32_div_set_value(div_id, div_n); in stm32_clk_configure_div()
1798 uint32_t val = stm32_div_get_value(cfg->div_id); in clk_stm32_composite_get_duty_cycle()
1959 .div_id = (NO_DIV),\
1989 .div_id = (_div_id),\
2071 .div_id = DIV_PLL1DIVP,
2087 .div_id = DIV_MPU,
2150 .div_id = DIV_AXI,
2162 .div_id = DIV_MLAHB,
H A Dclk-stm32mp15.c716 enum stm32mp1_div_id div_id) in stm32mp1_read_pll_freq() argument
723 if (div_id >= _DIV_NB) in stm32mp1_read_pll_freq()
727 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; in stm32mp1_read_pll_freq()
H A Dclk-stm32mp21.c1808 uint32_t div_id = 0; in stm32_clk_configure_div() local
1811 div_id = (data & DIV_ID_MASK) >> DIV_ID_SHIFT; in stm32_clk_configure_div()
1814 return stm32_div_set_value(div_id, div_n); in stm32_clk_configure_div()
2566 .div_id = (_div_id),\
2621 .div_id = (_div_id),\
H A Dclk-stm32mp25.c1812 uint32_t div_id = 0; in stm32_clk_configure_div() local
1815 div_id = (data & DIV_ID_MASK) >> DIV_ID_SHIFT; in stm32_clk_configure_div()
1818 return stm32_div_set_value(div_id, div_n); in stm32_clk_configure_div()
2568 .div_id = (_div_id),\
/optee_os/core/include/dt-bindings/clock/
H A Dstm32mp21-clksrc.h43 #define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
44 ((div_id) << DIV_ID_SHIFT |\
H A Dstm32mp25-clksrc.h70 #define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
71 ((div_id) << DIV_ID_SHIFT |\
H A Dstm32mp13-clksrc.h67 #define DIV(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
68 ((div_id) << DIV_ID_SHIFT) |\