| /optee_os/core/drivers/clk/ |
| H A D | clk-stm32-core.h | 181 #define STM32_FIXED_FACTOR(_name, _parent, _flags, _mult, _div)\ argument
191 .parents = { (_parent) },\
194 #define STM32_GATE(_name, _parent, _flags, _gate_id)\ argument
203 .parents = { (_parent) },\
206 #define STM32_DIVIDER(_name, _parent, _flags, _div_id)\ argument
215 .parents = { (_parent) },\
230 #define STM32_GATE_READY(_name, _parent, _flags, _gate_id)\ argument
239 .parents = { _parent },\
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| H A D | clk-stm32mp15.c | 244 #define _CLK_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ argument
252 .fixed = (_parent), \
268 #define _CLK_SC_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ argument
276 .fixed = (_parent), \
293 #define _CLK_SC2_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ argument
301 .fixed = (_parent), \
304 #define _CLK_PARENT(idx, _offset, _src, _mask, _parent) \ argument
309 .parent = (_parent), \
310 .nb_parent = ARRAY_SIZE(_parent) \
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| H A D | clk-stm32mp21.c | 2539 #define STM32_OSC_KERON(_name, _parent, _gate_id)\ argument
2547 .parents = { (_parent) },\
2550 #define STM32_HSE_DIV2(_name, _parent, _flags, _gate_id)\ argument
2559 .parents = { (_parent) },\
2562 #define STM32_HSE_RTC(_name, _parent, _flags, _div_id)\ argument
2571 .parents = { (_parent) },\
2765 #define STM32_TIMER(_name, _parent, _flags, _apbdiv, _timpre)\ argument
2775 .parents = { _parent },\
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| H A D | clk-stm32mp25.c | 2552 #define STM32_HSE_DIV2(_name, _parent, _flags, _gate_id)\ argument
2561 .parents = { (_parent) },\
2564 #define STM32_HSE_RTC(_name, _parent, _flags, _div_id)\ argument
2573 .parents = { (_parent) },\
2757 #define STM32_TIMER(_name, _parent, _flags, _apbdiv, _timpre)\ argument
2767 .parents = { _parent },\
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| H A D | clk-stm32mp13.c | 1941 #define STM32_TIMER(_name, _parent, _flags, _apbdiv, _timpre)\ argument
1951 .parents = { _parent },\
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