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Searched refs:MUX_MUXSEL6 (Results 1 – 8 of 8) sorted by relevance

/optee_os/core/include/dt-bindings/clock/
H A Dstm32mp21-clksrc.h71 #define MUX_MUXSEL6 6 macro
H A Dstm32mp25-clksrc.h97 #define MUX_MUXSEL6 6 macro
/optee_os/core/arch/arm/dts/
H A Dstm32mp215f-dk-ca35tdcid-rcc.dtsi129 src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>;
H A Dstm32mp235f-dk-ca35tdcid-rcc.dtsi129 src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>;
H A Dstm32mp257f-dk-ca35tdcid-rcc.dtsi136 src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>;
H A Dstm32mp257f-ev1-ca35tdcid-rcc.dtsi136 src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>;
/optee_os/core/drivers/clk/
H A Dclk-stm32mp21.c581 _MUX_CFG(MUX_MUXSEL6, RCC_MUXSELCFGR, 24, 2, MUX_NO_RDY),
997 CLK_PLL_CFG(PLL2_ID, GATE_PLL2, MUX_MUXSEL6, RCC_PLL2CFGR1),
2659 static STM32_PLL2(ck_pll2, 0, RCC_PLL2CFGR1, GATE_PLL2, MUX_MUXSEL6);
H A Dclk-stm32mp25.c616 _MUX_CFG(MUX_MUXSEL6, RCC_MUXSELCFGR, 24, 2, MUX_NO_RDY),
1015 CLK_PLL_CFG(PLL2_ID, GATE_PLL2, MUX_MUXSEL6, RCC_PLL2CFGR1),
2650 static STM32_PLL2(ck_pll2, 0, RCC_PLL2CFGR1, GATE_PLL2, MUX_MUXSEL6);