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Searched refs:MUX_MUXSEL5 (Results 1 – 8 of 8) sorted by relevance

/optee_os/core/arch/arm/dts/
H A Dstm32mp215f-dk-ca35tdcid-rcc.dtsi115 src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
120 src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
H A Dstm32mp235f-dk-ca35tdcid-rcc.dtsi115 src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
120 src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
H A Dstm32mp257f-dk-ca35tdcid-rcc.dtsi122 src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
127 src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
H A Dstm32mp257f-ev1-ca35tdcid-rcc.dtsi122 src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
127 src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
/optee_os/core/include/dt-bindings/clock/
H A Dstm32mp21-clksrc.h70 #define MUX_MUXSEL5 5 macro
H A Dstm32mp25-clksrc.h96 #define MUX_MUXSEL5 5 macro
/optee_os/core/drivers/clk/
H A Dclk-stm32mp21.c580 _MUX_CFG(MUX_MUXSEL5, RCC_MUXSELCFGR, 20, 2, MUX_NO_RDY),
996 CLK_PLL_CFG(PLL1_ID, GATE_PLL1, MUX_MUXSEL5, 0),
2658 static STM32_PLL1(ck_pll1, 0, MUX_MUXSEL5);
H A Dclk-stm32mp25.c615 _MUX_CFG(MUX_MUXSEL5, RCC_MUXSELCFGR, 20, 2, MUX_NO_RDY),
1014 CLK_PLL_CFG(PLL1_ID, GATE_PLL1, MUX_MUXSEL5, 0),
2649 static STM32_PLL1(ck_pll1, 0, MUX_MUXSEL5);