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Searched refs:MUX_MUXSEL4 (Results 1 – 8 of 8) sorted by relevance

/optee_os/core/include/dt-bindings/clock/
H A Dstm32mp21-clksrc.h69 #define MUX_MUXSEL4 4 macro
H A Dstm32mp25-clksrc.h95 #define MUX_MUXSEL4 4 macro
/optee_os/core/arch/arm/dts/
H A Dstm32mp215f-dk-ca35tdcid-rcc.dtsi175 src = <MUX_CFG(MUX_MUXSEL4, MUXSEL_HSE)>;
H A Dstm32mp235f-dk-ca35tdcid-rcc.dtsi184 src = <MUX_CFG(MUX_MUXSEL4, MUXSEL_HSE)>;
H A Dstm32mp257f-dk-ca35tdcid-rcc.dtsi196 src = <MUX_CFG(MUX_MUXSEL4, MUXSEL_HSE)>;
H A Dstm32mp257f-ev1-ca35tdcid-rcc.dtsi196 src = <MUX_CFG(MUX_MUXSEL4, MUXSEL_HSE)>;
/optee_os/core/drivers/clk/
H A Dclk-stm32mp21.c579 _MUX_CFG(MUX_MUXSEL4, RCC_MUXSELCFGR, 16, 2, GATE_PLL8_CKREFST),
1002 CLK_PLL_CFG(PLL8_ID, GATE_PLL8, MUX_MUXSEL4, RCC_PLL8CFGR1),
2664 static STM32_PLLS(ck_pll8, 0, RCC_PLL8CFGR1, GATE_PLL8, MUX_MUXSEL4);
H A Dclk-stm32mp25.c614 _MUX_CFG(MUX_MUXSEL4, RCC_MUXSELCFGR, 16, 2, GATE_PLL8_CKREFST),
1021 CLK_PLL_CFG(PLL8_ID, GATE_PLL8, MUX_MUXSEL4, RCC_PLL8CFGR1),
2656 static STM32_PLLS(ck_pll8, 0, RCC_PLL8CFGR1, GATE_PLL8, MUX_MUXSEL4);