Home
last modified time | relevance | path

Searched refs:MUX_MUXSEL3 (Results 1 – 8 of 8) sorted by relevance

/optee_os/core/include/dt-bindings/clock/
H A Dstm32mp21-clksrc.h68 #define MUX_MUXSEL3 3 macro
H A Dstm32mp25-clksrc.h94 #define MUX_MUXSEL3 3 macro
/optee_os/core/arch/arm/dts/
H A Dstm32mp215f-dk-ca35tdcid-rcc.dtsi165 src = <MUX_CFG(MUX_MUXSEL3, MUXSEL_HSE)>;
H A Dstm32mp235f-dk-ca35tdcid-rcc.dtsi174 src = <MUX_CFG(MUX_MUXSEL3, MUXSEL_HSE)>;
H A Dstm32mp257f-dk-ca35tdcid-rcc.dtsi186 src = <MUX_CFG(MUX_MUXSEL3, MUXSEL_HSE)>;
H A Dstm32mp257f-ev1-ca35tdcid-rcc.dtsi186 src = <MUX_CFG(MUX_MUXSEL3, MUXSEL_HSE)>;
/optee_os/core/drivers/clk/
H A Dclk-stm32mp21.c578 _MUX_CFG(MUX_MUXSEL3, RCC_MUXSELCFGR, 12, 2, GATE_PLL7_CKREFST),
1001 CLK_PLL_CFG(PLL7_ID, GATE_PLL7, MUX_MUXSEL3, RCC_PLL7CFGR1),
2663 static STM32_PLLS(ck_pll7, 0, RCC_PLL7CFGR1, GATE_PLL7, MUX_MUXSEL3);
H A Dclk-stm32mp25.c613 _MUX_CFG(MUX_MUXSEL3, RCC_MUXSELCFGR, 12, 2, GATE_PLL7_CKREFST),
1020 CLK_PLL_CFG(PLL7_ID, GATE_PLL7, MUX_MUXSEL3, RCC_PLL7CFGR1),
2655 static STM32_PLLS(ck_pll7, 0, RCC_PLL7CFGR1, GATE_PLL7, MUX_MUXSEL3);