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Searched refs:MUX_MUXSEL1 (Results 1 – 8 of 8) sorted by relevance

/optee_os/core/include/dt-bindings/clock/
H A Dstm32mp21-clksrc.h66 #define MUX_MUXSEL1 1 macro
H A Dstm32mp25-clksrc.h92 #define MUX_MUXSEL1 1 macro
/optee_os/core/arch/arm/dts/
H A Dstm32mp215f-dk-ca35tdcid-rcc.dtsi147 src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>;
H A Dstm32mp235f-dk-ca35tdcid-rcc.dtsi156 src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>;
H A Dstm32mp257f-dk-ca35tdcid-rcc.dtsi168 src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>;
H A Dstm32mp257f-ev1-ca35tdcid-rcc.dtsi168 src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>;
/optee_os/core/drivers/clk/
H A Dclk-stm32mp21.c576 _MUX_CFG(MUX_MUXSEL1, RCC_MUXSELCFGR, 4, 2, GATE_PLL5_CKREFST),
999 CLK_PLL_CFG(PLL5_ID, GATE_PLL5, MUX_MUXSEL1, RCC_PLL5CFGR1),
2661 static STM32_PLLS(ck_pll5, 0, RCC_PLL5CFGR1, GATE_PLL5, MUX_MUXSEL1);
H A Dclk-stm32mp25.c611 _MUX_CFG(MUX_MUXSEL1, RCC_MUXSELCFGR, 4, 2, GATE_PLL5_CKREFST),
1018 CLK_PLL_CFG(PLL5_ID, GATE_PLL5, MUX_MUXSEL1, RCC_PLL5CFGR1),
2653 static STM32_PLLS(ck_pll5, 0, RCC_PLL5CFGR1, GATE_PLL5, MUX_MUXSEL1);