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Searched refs:MUX_MUXSEL0 (Results 1 – 8 of 8) sorted by relevance

/optee_os/core/include/dt-bindings/clock/
H A Dstm32mp21-clksrc.h65 #define MUX_MUXSEL0 0 macro
H A Dstm32mp25-clksrc.h91 #define MUX_MUXSEL0 0 macro
/optee_os/core/arch/arm/dts/
H A Dstm32mp215f-dk-ca35tdcid-rcc.dtsi138 src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>;
H A Dstm32mp235f-dk-ca35tdcid-rcc.dtsi147 src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>;
H A Dstm32mp257f-dk-ca35tdcid-rcc.dtsi159 src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>;
H A Dstm32mp257f-ev1-ca35tdcid-rcc.dtsi159 src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>;
/optee_os/core/drivers/clk/
H A Dclk-stm32mp21.c575 _MUX_CFG(MUX_MUXSEL0, RCC_MUXSELCFGR, 0, 2, GATE_PLL4_CKREFST),
998 CLK_PLL_CFG(PLL4_ID, GATE_PLL4, MUX_MUXSEL0, RCC_PLL4CFGR1),
2660 static STM32_PLLS(ck_pll4, 0, RCC_PLL4CFGR1, GATE_PLL4, MUX_MUXSEL0);
H A Dclk-stm32mp25.c610 _MUX_CFG(MUX_MUXSEL0, RCC_MUXSELCFGR, 0, 2, GATE_PLL4_CKREFST),
1017 CLK_PLL_CFG(PLL4_ID, GATE_PLL4, MUX_MUXSEL0, RCC_PLL4CFGR1),
2652 static STM32_PLLS(ck_pll4, 0, RCC_PLL4CFGR1, GATE_PLL4, MUX_MUXSEL0);