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Searched refs:CSU_BASE (Results 1 – 10 of 10) sorted by relevance

/optee_os/core/include/drivers/
H A Dzynqmp_csu.h27 #define ZYNQMP_CSU_AES_BASE (CSU_BASE + 0x1000)
31 #define ZYNQMP_CSU_SHA_BASE (CSU_BASE + 0x2000)
35 #define ZYNQMP_CSU_PCAP_BASE (CSU_BASE + 0x3000)
39 #define ZYNQMP_CSU_PUF_BASE (CSU_BASE + 0x4000)
43 #define ZYNQMP_CSU_TAMPER_BASE (CSU_BASE + 0x5000)
/optee_os/core/arch/arm/plat-ls/
H A Dmain.c95 for (addr = CSU_BASE + CSU_CSL_START; in plat_primary_init_early()
96 addr != CSU_BASE + CSU_CSL_END; in plat_primary_init_early()
101 io_write32(CSU_BASE + CSU_CSL30, in plat_primary_init_early()
103 io_write32(CSU_BASE + CSU_CSL37, in plat_primary_init_early()
107 for (addr = CSU_BASE + CSU_CSL_START; in plat_primary_init_early()
108 addr != CSU_BASE + CSU_CSL_END; in plat_primary_init_early()
/optee_os/core/arch/arm/plat-zynqmp/
H A Dmain.c63 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CSU_BASE, CSU_SIZE);
93 vaddr_t csu = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, CSU_SIZE); in plat_rpmb_key_is_ready()
H A Dplatform_config.h82 #define CSU_BASE 0xFFCA0000 macro
/optee_os/core/drivers/
H A Dzynqmp_csu_puf.c33 vaddr_t csu = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, CSU_SIZE); in zynqmp_csu_puf_regenerate()
63 vaddr_t csu = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, CSU_SIZE); in zynqmp_csu_puf_init()
H A Dimx_csu.c109 csu_base = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, 1); in csu_configure()
H A Dzynqmp_huk.c108 vaddr_t csu = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, CSU_SIZE); in tee_otp_get_hw_unique_key()
H A Dzynqmp_csu_aes.c211 vaddr_t csu = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, CSU_SIZE); in aes_prepare_op()
/optee_os/core/arch/arm/plat-imx/registers/
H A Dimx7.h46 #define CSU_BASE 0x303E0000 macro
H A Dimx6.h51 #define CSU_BASE 0x021C0000 macro