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Searched refs:BIT32 (Results 1 – 25 of 66) sorted by relevance

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/optee_os/core/arch/arm/plat-imx/registers/
H A Dimx6-dcp.h52 #define DCP_CTRL_SFTRST BIT32(31)
53 #define DCP_CTRL_CLKGATE BIT32(30)
54 #define DCP_CTRL_GATHER_RESIDUAL_WRITES BIT32(23)
55 #define DCP_CTRL_ENABLE_CONTEXT_CACHING BIT32(22)
56 #define DCP_CTRL_ENABLE_CONTEXT_SWITCHING BIT32(21)
57 #define DCP_CTRL_CH3_INTERRUPT_ENABLE BIT32(3)
58 #define DCP_CTRL_CH2_INTERRUPT_ENABLE BIT32(2)
59 #define DCP_CTRL_CH1_INTERRUPT_ENABLE BIT32(1)
60 #define DCP_CTRL_CH0_INTERRUPT_ENABLE BIT32(0)
63 #define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY BIT32(29)
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H A Dimx6-crm.h87 #define BM_CCM_CCR_RBC_EN BIT32(BS_CCM_CCR_RBC_EN)
99 #define BM_CCM_CCDR_MMDC_CH1_HS_MASK BIT32(BS_CCM_CCDR_MMDC_CH1_HS_MASK)
101 #define BM_CCM_CCDR_MMDC_CH0_HS_MASK BIT32(BS_CCM_CCDR_MMDC_CH0_HS_MASK)
105 #define BM_CCM_CSR_COSC_READY BIT32(BS_CCM_CSR_COSC_READY)
107 #define BM_CCM_CSR_REF_EN_B BIT32(BS_CCM_CSR_REF_EN_B)
111 #define BM_CCM_CCSR_PDF_540M_AUTO_DIS BIT32(BS_CCM_CCSR_PDF_540M_AUTO_DIS)
113 #define BM_CCM_CCSR_PDF_720M_AUTO_DIS BIT32(BS_CCM_CCSR_PDF_720M_AUTO_DIS)
115 #define BM_CCM_CCSR_PDF_454M_AUTO_DIS BIT32(BS_CCM_CCSR_PDF_454M_AUTO_DIS)
117 #define BM_CCM_CCSR_PDF_508M_AUTO_DIS BIT32(BS_CCM_CCSR_PDF_508M_AUTO_DIS)
119 #define BM_CCM_CCSR_PDF_594M_AUTO_DIS BIT32(BS_CCM_CCSR_PDF_594M_AUTO_DIS)
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H A Dimx7ulp-crm.h12 #define PCC_ENABLE_CLOCK BIT32(PCC_CGC_BIT_SHIFT)
13 #define PCC_DISABLE_CLOCK BIT32(0)
/optee_os/core/arch/arm/include/
H A Darm32.h35 #define PMCR_DP BIT32(5)
37 #define SCR_NS BIT32(0)
38 #define SCR_IRQ BIT32(1)
39 #define SCR_FIQ BIT32(2)
40 #define SCR_EA BIT32(3)
41 #define SCR_FW BIT32(4)
42 #define SCR_AW BIT32(5)
43 #define SCR_NET BIT32(6)
44 #define SCR_SCD BIT32(7)
45 #define SCR_HCE BIT32(8)
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/optee_os/core/drivers/crypto/caam/include/
H A Dcaam_desc_ccb_defines.h11 #define CCTRL_ULOAD_PKHA_B BIT32(27)
12 #define CCTRL_ULOAD_PKHA_A BIT32(26)
15 #define CLR_WR_IFIFO_NFIFO BIT32(31)
16 #define CLR_WR_RST_C1_CHA BIT32(29)
17 #define CLR_WR_RST_C2_CHA BIT32(28)
18 #define CLR_WR_RST_C1_DNE BIT32(27)
19 #define CLR_WR_RST_C2_CTX BIT32(21)
20 #define CLR_WR_RST_C2_DSZ BIT32(18)
21 #define CLR_WR_RST_C1_DSZ BIT32(2)
22 #define CLR_WR_RST_C1_MDE BIT32(0)
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H A Dcaam_trace.h28 #define DBG_TRACE_HAL BIT32(0) /* HAL trace */
29 #define DBG_TRACE_CTRL BIT32(1) /* Controller trace */
30 #define DBG_TRACE_MEM BIT32(2) /* Memory utility trace */
31 #define DBG_TRACE_SGT BIT32(3) /* Scatter Gather trace */
32 #define DBG_TRACE_PWR BIT32(4) /* Power trace */
33 #define DBG_TRACE_JR BIT32(5) /* Job Ring trace */
34 #define DBG_TRACE_RNG BIT32(6) /* RNG trace */
35 #define DBG_TRACE_HASH BIT32(7) /* Hash trace */
36 #define DBG_TRACE_RSA BIT32(8) /* RSA trace */
37 #define DBG_TRACE_CIPHER BIT32(9) /* Cipher dump Buffer */
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H A Dcaam_desc_defines.h23 #define CMD_SGT BIT32(24)
24 #define CMD_IMM BIT32(23)
32 #define HDR_JD_ONE BIT32(23)
54 #define KEY_PTS BIT32(14)
142 #define FIFO_LOAD_EXT BIT32(22)
187 #define FIFO_STORE_EXT BIT32(22)
240 #define MOVE_WC BIT32(24)
331 #define PROT_RSA_FINISH_KEY_ENC_OUT_ECB BIT32(6)
332 #define PROT_RSA_FINISH_KEY_ENC_OUT_CCM BIT32(6)
336 #define PROT_RSA_FINISH_KEY_ENC_CCM BIT32(4)
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/optee_os/core/drivers/crypto/caam/hal/imx_6_7/registers/
H A Dctrl_regs.h14 #define MCFGR_WDE BIT32(30)
25 #define JRxMIDR_MS_LMID BIT32(31)
26 #define JRxMIDR_MS_LAMTD BIT32(17)
27 #define JRxMIDR_MS_AMTD BIT32(16)
29 #define JRxMIDR_MS_JROWN_NS BIT32(3)
32 #define JRxMIDR_LS_NONSEQ_NS BIT32(19)
34 #define JRxMIDR_LS_SEQ_NS BIT32(3)
37 #define JRxMIDR_MS_JROWN_NS BIT32(4)
40 #define JRxMIDR_LS_NONSEQ_NS BIT32(20)
42 #define JRxMIDR_LS_SEQ_NS BIT32(4)
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/optee_os/core/drivers/crypto/caam/hal/ls/registers/
H A Dctrl_regs.h14 #define MCFGR_WDE BIT32(30)
25 #define JRxMIDR_MS_LMID BIT32(31)
26 #define JRxMIDR_MS_LAMTD BIT32(17)
27 #define JRxMIDR_MS_TZ BIT32(15)
28 #define JRxMIDR_MS_AMTD BIT32(16)
29 #define JRxMIDR_MS_JROWN_NS BIT32(3)
32 #define JRxMIDR_LS_NONSEQ_NS BIT32(19)
34 #define JRxMIDR_LS_SEQ_NS BIT32(3)
/optee_os/core/drivers/crypto/caam/hal/common/registers/
H A Djr_regs.h46 #define JRX_JRINTR_JRI BIT32(0)
52 #define JRX_JRCFGR_LS_ICEN BIT32(1)
53 #define JRX_JRCFGR_LS_IMSK BIT32(0)
63 #define JRX_JRCR_PARK BIT32(1)
64 #define JRX_JRCR_RESET BIT32(0)
68 #define JRX_CSTA_TRNG_IDLE BIT32(2)
69 #define JRX_CSTA_IDLE BIT32(1)
70 #define JRX_CSTA_BSY BIT32(0)
H A Drng_regs.h17 #define TRNG_MCTL_PRGM BIT32(16)
18 #define TRNG_MCTL_ERR BIT32(12)
19 #define TRNG_MCTL_ACC BIT32(5)
115 #define RNG_STA_SKVN BIT32(30)
116 #define RNG_STA_IF1 BIT32(1)
117 #define RNG_STA_IF0 BIT32(0)
118 #define RNG_STA_PR0 BIT32(4)
119 #define RNG_STA_PR1 BIT32(5)
H A Dsm_regs.h14 #define SM_SMAPR_CSP BIT32(15)
15 #define SM_SMAPR_SMAP_LCK BIT32(13)
16 #define SM_SMAPR_SMAG_LCK BIT32(12)
/optee_os/core/drivers/crypto/caam/hal/imx_8ulp/registers/
H A Dctrl_regs.h14 #define MCFGR_WDE BIT32(30)
23 #define JRxDID_MS_LDID BIT32(31)
25 #define JRxDID_MS_LAMTD BIT32(17)
26 #define JRxDID_MS_AMTD BIT32(16)
27 #define JRxDID_MS_TZ_OWN BIT32(15)
28 #define JRxDID_MS_PRIM_TZ BIT32(4)
35 #define BM_SCFGR_MPMRL BIT32(26)
/optee_os/core/drivers/crypto/caam/hal/imx_8m/registers/
H A Dctrl_regs.h14 #define MCFGR_WDE BIT32(30)
23 #define JRxDID_MS_LDID BIT32(31)
25 #define JRxDID_MS_LAMTD BIT32(17)
26 #define JRxDID_MS_AMTD BIT32(16)
27 #define JRxDID_MS_TZ_OWN BIT32(15)
28 #define JRxDID_MS_PRIM_TZ BIT32(4)
35 #define BM_SCFGR_MPMRL BIT32(26)
/optee_os/lib/libutee/include/
H A Duser_ta_header.h13 #define TA_FLAG_USER_MODE 0 /* Deprecated, was BIT32(0) */
14 #define TA_FLAG_EXEC_DDR 0 /* Deprecated, was BIT32(1) */
15 #define TA_FLAG_SINGLE_INSTANCE BIT32(2)
16 #define TA_FLAG_MULTI_SESSION BIT32(3)
17 #define TA_FLAG_INSTANCE_KEEP_ALIVE BIT32(4) /* remains after last close */
18 #define TA_FLAG_SECURE_DATA_PATH BIT32(5) /* accesses SDP memory */
19 #define TA_FLAG_REMAP_SUPPORT 0 /* Deprecated, was BIT32(6) */
20 #define TA_FLAG_CACHE_MAINTENANCE BIT32(7) /* use cache flush syscall */
25 #define TA_FLAG_CONCURRENT BIT32(8)
48 #define TA_FLAG_DEVICE_ENUM BIT32(
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H A Dpta_system.h54 #define PTA_SYSTEM_MAP_FLAG_SHAREABLE BIT32(0)
56 #define PTA_SYSTEM_MAP_FLAG_WRITEABLE BIT32(1)
58 #define PTA_SYSTEM_MAP_FLAG_EXECUTABLE BIT32(2)
H A Dpta_scmi_client.h76 #define PTA_SCMI_CAPS_SMT_HEADER BIT32(0)
79 #define PTA_SCMI_CAPS_MSG_HEADER BIT32(1)
/optee_os/core/drivers/crypto/caam/hal/imx_8q/registers/
H A Dctrl_regs.h18 #define JRxDID_MS_LDID BIT32(31)
20 #define JRxDID_MS_LAMTD BIT32(17)
21 #define JRxDID_MS_AMTD BIT32(16)
22 #define JRxDID_MS_TZ_OWN BIT32(15)
23 #define JRxDID_MS_PRIM_TZ BIT32(4)
30 #define BM_SCFGR_MPMRL BIT32(26)
/optee_os/core/include/drivers/
H A Datmel_shdwc.h29 #define AT91_SHDW_RTCWKEN BIT32(17)
30 #define AT91_SHDW_RTTWKEN BIT32(16)
36 #define AT91_SHDW_WKUPIS(x) (BIT32((x) + AT91_SHDW_WKUPIS_SHIFT))
41 #define AT91_SHDW_WKUPEN(x) (BIT32(x) & AT91_SHDW_WKUPEN_MASK)
44 #define AT91_SHDW_WKUPT(x) (BIT32((x) + AT91_SHDW_WKUPT_SHIFT))
/optee_os/core/arch/arm/include/kernel/
H A Dtz_ssvce_def.h86 #define PL310_CTRL_ENABLE_BIT BIT32(0)
87 #define PL310_AUX_16WAY_BIT BIT32(16)
108 #define SCU_ACCESS_CONTROL_CPU0 BIT32(0)
109 #define SCU_ACCESS_CONTROL_CPU1 BIT32(1)
110 #define SCU_ACCESS_CONTROL_CPU2 BIT32(2)
111 #define SCU_ACCESS_CONTROL_CPU3 BIT32(3)
/optee_os/core/drivers/
H A Dgic.c59 #define GICD_CTLR_ENABLEGRP0 BIT32(0)
60 #define GICD_CTLR_ENABLEGRP1NS BIT32(1)
61 #define GICD_CTLR_ENABLEGRP1S BIT32(2)
62 #define GICD_CTLR_ARE_S BIT32(4)
63 #define GICD_CTLR_ARE_NS BIT32(5)
80 #define GICR_CTLR_RWP BIT32(3)
218 if (BIT32(b) & reg) { in probe_max_it()
266 if (!(BIT32(n) & (grp0 ^ gd->per_cpu_group_status)) && in gicv3_sync_redist_config()
267 !(BIT32(n) & (gmod0 ^ gd->per_cpu_group_modifier))) in gicv3_sync_redist_config()
276 io_write32(gicr_base + GICR_ICENABLER0, BIT32(n)); in gicv3_sync_redist_config()
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/optee_os/core/arch/arm/plat-sunxi/
H A Dpsci.c101 io_clrbits32(cpucfg + REG_CPUCFG_GEN_CTRL, BIT32(core_idx)); in psci_cpu_on()
105 io_clrbits32(cpucfg + REG_CPUCFG_DBG_CTRL1, BIT32(core_idx)); in psci_cpu_on()
118 io_clrbits32(base + REG_PRCM_CPU_PWROFF, BIT32(core_idx)); in psci_cpu_on()
127 io_setbits32(cpucfg + REG_CPUCFG_DBG_CTRL1, BIT32(core_idx)); in psci_cpu_on()
154 io_setbits32(base + REG_PRCM_CPU_PWROFF, BIT32(core_id)); in psci_cpu_off()
/optee_os/ldelf/include/
H A Dldelf.h112 #define LDELF_MAP_FLAG_SHAREABLE BIT32(0)
113 #define LDELF_MAP_FLAG_WRITEABLE BIT32(1)
114 #define LDELF_MAP_FLAG_EXECUTABLE BIT32(2)
115 #define LDELF_MAP_FLAG_BTI BIT32(3)
/optee_os/core/drivers/pm/imx/
H A Dsrc.c22 #define SRC_SCR_CORE1_RST_BIT(_cpu) BIT32(14 + (_cpu) - 1)
23 #define SRC_SCR_CORE1_ENABLE_BIT(_cpu) BIT32(22 + (_cpu) - 1)
24 #define SRC_A7RCR0_A7_CORE_RESET0_BIT(_cpu) BIT32((_cpu) - 1)
25 #define SRC_A7RCR1_A7_CORE1_ENABLE_BIT(_cpu) BIT32(1 + (_cpu) - 1)
/optee_os/core/arch/arm/plat-stm/
H A Drng_support.c19 #define RNG_STATUS_ERR0 BIT32(0)
20 #define RNG_STATUS_ERR1 BIT32(1)
21 #define RNG_STATUS_FULL BIT32(5)

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