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Searched refs:val32 (Results 1 – 25 of 353) sorted by relevance

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/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/mac/mac_ax/
H A Drx_forwarding.c127 u32 val32; in af_fwd_cfg() local
130 val32 = MAC_REG_R32(R_AX_ACTION_FWD0); in af_fwd_cfg()
133 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_CSA); in af_fwd_cfg()
136 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDTS_REQ); in af_fwd_cfg()
139 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDTS_RES); in af_fwd_cfg()
142 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_DELTS); in af_fwd_cfg()
145 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDBA_REQ); in af_fwd_cfg()
148 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDBA_RES); in af_fwd_cfg()
151 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_DELBA); in af_fwd_cfg()
154 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_NCW); in af_fwd_cfg()
[all …]
H A Dtrxcfg.c44 u32 val32, reg; in scheduler_imr_enable() local
48 val32 = MAC_REG_R32(reg); in scheduler_imr_enable()
49 val32 &= ~(B_AX_SORT_NON_IDLE_ERR_INT_EN | in scheduler_imr_enable()
51 val32 |= ((B_AX_SORT_NON_IDLE_ERR_INT_EN & in scheduler_imr_enable()
55 MAC_REG_W32(reg, val32); in scheduler_imr_enable()
62 u32 val32, reg; in ptcl_imr_enable() local
66 val32 = 0; in ptcl_imr_enable()
67 val32 &= ~(B_AX_FSM_TIMEOUT_ERR_INT_EN | in ptcl_imr_enable()
85 val32 |= ((B_AX_FSM_TIMEOUT_ERR_INT_EN & in ptcl_imr_enable()
119 MAC_REG_W32(reg, val32); in ptcl_imr_enable()
[all …]
H A Ddbgport_hw.c23 u32 val32, intn_val; in dp_intn_idx_set() local
57 val32 = MAC_REG_R32(R_AX_PCIE_DBG_CTRL); in dp_intn_idx_set()
58 val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); in dp_intn_idx_set()
59 MAC_REG_W32(R_AX_PCIE_DBG_CTRL, val32); in dp_intn_idx_set()
72 val32 = MAC_REG_R32(R_AX_PCIE_DBG_CTRL); in dp_intn_idx_set()
73 val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); in dp_intn_idx_set()
74 MAC_REG_W32(R_AX_PCIE_DBG_CTRL, val32); in dp_intn_idx_set()
84 val32 = MAC_REG_R32(R_AX_PCIE_DBG_CTRL); in dp_intn_idx_set()
85 val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); in dp_intn_idx_set()
86 MAC_REG_W32(R_AX_PCIE_DBG_CTRL, val32); in dp_intn_idx_set()
[all …]
H A Drx_filter.c97 u32 val32 = 0x0; in rx_fltr_opt_2_uint() local
100 val32 = in rx_fltr_opt_2_uint()
136 *mac_fltr_value = val32; in rx_fltr_opt_2_uint()
164 u32 val32; in mac_get_rx_fltr_opt() local
166 val32 = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); in mac_get_rx_fltr_opt()
167 if (val32 != MACSUCCESS) { in mac_get_rx_fltr_opt()
169 return val32; in mac_get_rx_fltr_opt()
177 val32 = MAC_REG_R32((band == MAC_AX_BAND_1) ? in mac_get_rx_fltr_opt()
179 fltr_opt->sniffer_mode = ((val32 & B_AX_SNIFFER_MODE) != 0); in mac_get_rx_fltr_opt()
180 fltr_opt->acpt_a1_match_pkt = ((val32 & B_AX_A_A1_MATCH) != 0); in mac_get_rx_fltr_opt()
[all …]
H A Dhci_fc.c1115 u32 val32 = 0; in hfc_ch_ctrl() local
1128 val32 = SET_WORD(cfg[MAC_AX_DMA_ACH0].min, B_AX_ACH0_MIN_PG) | in hfc_ch_ctrl()
1133 MAC_REG_W32(R_AX_ACH0_PAGE_CTRL_V1, val32); in hfc_ch_ctrl()
1135 MAC_REG_W32(R_AX_ACH0_PAGE_CTRL, val32); in hfc_ch_ctrl()
1139 val32 = SET_WORD(cfg[MAC_AX_DMA_ACH1].min, B_AX_ACH1_MIN_PG) | in hfc_ch_ctrl()
1144 MAC_REG_W32(R_AX_ACH1_PAGE_CTRL_V1, val32); in hfc_ch_ctrl()
1146 MAC_REG_W32(R_AX_ACH1_PAGE_CTRL, val32); in hfc_ch_ctrl()
1150 val32 = SET_WORD(cfg[MAC_AX_DMA_ACH2].min, B_AX_ACH2_MIN_PG) | in hfc_ch_ctrl()
1155 MAC_REG_W32(R_AX_ACH2_PAGE_CTRL_V1, val32); in hfc_ch_ctrl()
1157 MAC_REG_W32(R_AX_ACH2_PAGE_CTRL, val32); in hfc_ch_ctrl()
[all …]
H A Ddbgpkg.c1639 u32 base_addr, strt_pg, residue, i, cnt, val32; in __dump_mac_mem() local
1681 val32 = le32_to_cpu(MAC_REG_R32(i)); in __dump_mac_mem()
1683 *(u32 *)(buf + cnt) = val32; in __dump_mac_mem()
1688 val32); in __dump_mac_mem()
1810 u32 i, j, k, page, val32; in __dump_reg_range() local
1818 val32 = MAC_REG_R32(j + 4 * k); in __dump_reg_range()
1819 PLTFM_MSG_ALWAYS("%08x ", val32); in __dump_reg_range()
1928 u32 val32; in dbg_port_sel() local
1960 val32 = MAC_REG_R32(R_AX_SCH_DBG_SEL); in dbg_port_sel()
1961 val32 |= B_AX_SCH_DBG_EN; in dbg_port_sel()
[all …]
H A Dmport.c344 u32 val32; in _get_port_cfg() local
375 val32 = MAC_REG_R32(cfg_regl[band][port]); in _get_port_cfg()
378 para->val = GET_FIELD(val32, B_AX_NET_TYPE_P0); in _get_port_cfg()
381 para->val = GET_FIELD(val32, B_AX_NET_TYPE_P1); in _get_port_cfg()
384 para->val = GET_FIELD(val32, B_AX_NET_TYPE_P2); in _get_port_cfg()
387 para->val = GET_FIELD(val32, B_AX_NET_TYPE_P3); in _get_port_cfg()
390 para->val = GET_FIELD(val32, B_AX_NET_TYPE_P4); in _get_port_cfg()
396 val32 = MAC_REG_R32(cfg_regl[band][port]); in _get_port_cfg()
397 if (val32 & b_en_l[port]) in _get_port_cfg()
404 val32 = MAC_REG_R32(bcnspc_regl[band][port]); in _get_port_cfg()
[all …]
H A Dla_mode.c21 u32 val32; in mac_lamode_cfg() local
23 val32 = MAC_REG_R32(R_AX_DMAC_FUNC_EN); in mac_lamode_cfg()
24 val32 |= B_AX_BBRPT_EN; in mac_lamode_cfg()
25 MAC_REG_W32(R_AX_DMAC_FUNC_EN, val32); in mac_lamode_cfg()
27 val32 = MAC_REG_R32(R_AX_DMAC_CLK_EN); in mac_lamode_cfg()
28 val32 |= B_AX_BBRPT_CLK_EN; in mac_lamode_cfg()
29 MAC_REG_W32(R_AX_DMAC_CLK_EN, val32); in mac_lamode_cfg()
31 val32 = MAC_REG_R32(R_AX_LA_CFG); in mac_lamode_cfg()
32 val32 &= ~BITS_AX_LA_CFG; in mac_lamode_cfg()
33 val32 |= ((cfg->la_func_en ? B_AX_LA_FEN : 0) | in mac_lamode_cfg()
[all …]
H A Dpwr.c35 u32 val32; in clr_aon_int() local
40 val32 = MAC_REG_R32(R_AX_FWS0IMR); in clr_aon_int()
41 val32 &= ~B_AX_FS_GPIOA_INT_EN; in clr_aon_int()
42 MAC_REG_W32(R_AX_FWS0IMR, val32); in clr_aon_int()
44 val32 = MAC_REG_R32(R_AX_FWS0ISR); in clr_aon_int()
45 val32 |= B_AX_FS_GPIOA_INT; in clr_aon_int()
46 MAC_REG_W32(R_AX_FWS0ISR, val32); in clr_aon_int()
53 u32 val32, cnt, ret = MACSUCCESS; in _patch_aon_int_leave_lps() local
60 val32 = MAC_REG_R32(R_AX_FWS0IMR); in _patch_aon_int_leave_lps()
61 val32 |= B_AX_FS_GPIOA_INT_EN; in _patch_aon_int_leave_lps()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/mac/mac_ax/
H A Drx_forwarding.c127 u32 val32; in af_fwd_cfg() local
130 val32 = MAC_REG_R32(R_AX_ACTION_FWD0); in af_fwd_cfg()
133 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_CSA); in af_fwd_cfg()
136 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDTS_REQ); in af_fwd_cfg()
139 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDTS_RES); in af_fwd_cfg()
142 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_DELTS); in af_fwd_cfg()
145 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDBA_REQ); in af_fwd_cfg()
148 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDBA_RES); in af_fwd_cfg()
151 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_DELBA); in af_fwd_cfg()
154 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_NCW); in af_fwd_cfg()
[all …]
H A Dtrxcfg.c44 u32 val32, reg; in scheduler_imr_enable() local
48 val32 = MAC_REG_R32(reg); in scheduler_imr_enable()
49 val32 &= ~(B_AX_SORT_NON_IDLE_ERR_INT_EN | in scheduler_imr_enable()
51 val32 |= ((B_AX_SORT_NON_IDLE_ERR_INT_EN & in scheduler_imr_enable()
55 MAC_REG_W32(reg, val32); in scheduler_imr_enable()
62 u32 val32, reg; in ptcl_imr_enable() local
66 val32 = 0; in ptcl_imr_enable()
67 val32 &= ~(B_AX_FSM_TIMEOUT_ERR_INT_EN | in ptcl_imr_enable()
85 val32 |= ((B_AX_FSM_TIMEOUT_ERR_INT_EN & in ptcl_imr_enable()
119 MAC_REG_W32(reg, val32); in ptcl_imr_enable()
[all …]
H A Ddbgport_hw.c23 u32 val32, intn_val; in dp_intn_idx_set() local
57 val32 = MAC_REG_R32(R_AX_PCIE_DBG_CTRL); in dp_intn_idx_set()
58 val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); in dp_intn_idx_set()
59 MAC_REG_W32(R_AX_PCIE_DBG_CTRL, val32); in dp_intn_idx_set()
72 val32 = MAC_REG_R32(R_AX_PCIE_DBG_CTRL); in dp_intn_idx_set()
73 val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); in dp_intn_idx_set()
74 MAC_REG_W32(R_AX_PCIE_DBG_CTRL, val32); in dp_intn_idx_set()
84 val32 = MAC_REG_R32(R_AX_PCIE_DBG_CTRL); in dp_intn_idx_set()
85 val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); in dp_intn_idx_set()
86 MAC_REG_W32(R_AX_PCIE_DBG_CTRL, val32); in dp_intn_idx_set()
[all …]
H A Drx_filter.c97 u32 val32 = 0x0; in rx_fltr_opt_2_uint() local
100 val32 = in rx_fltr_opt_2_uint()
136 *mac_fltr_value = val32; in rx_fltr_opt_2_uint()
164 u32 val32; in mac_get_rx_fltr_opt() local
166 val32 = check_mac_en(adapter, band, MAC_AX_CMAC_SEL); in mac_get_rx_fltr_opt()
167 if (val32 != MACSUCCESS) { in mac_get_rx_fltr_opt()
169 return val32; in mac_get_rx_fltr_opt()
177 val32 = MAC_REG_R32((band == MAC_AX_BAND_1) ? in mac_get_rx_fltr_opt()
179 fltr_opt->sniffer_mode = ((val32 & B_AX_SNIFFER_MODE) != 0); in mac_get_rx_fltr_opt()
180 fltr_opt->acpt_a1_match_pkt = ((val32 & B_AX_A_A1_MATCH) != 0); in mac_get_rx_fltr_opt()
[all …]
H A Dhci_fc.c1115 u32 val32 = 0; in hfc_ch_ctrl() local
1128 val32 = SET_WORD(cfg[MAC_AX_DMA_ACH0].min, B_AX_ACH0_MIN_PG) | in hfc_ch_ctrl()
1133 MAC_REG_W32(R_AX_ACH0_PAGE_CTRL_V1, val32); in hfc_ch_ctrl()
1135 MAC_REG_W32(R_AX_ACH0_PAGE_CTRL, val32); in hfc_ch_ctrl()
1139 val32 = SET_WORD(cfg[MAC_AX_DMA_ACH1].min, B_AX_ACH1_MIN_PG) | in hfc_ch_ctrl()
1144 MAC_REG_W32(R_AX_ACH1_PAGE_CTRL_V1, val32); in hfc_ch_ctrl()
1146 MAC_REG_W32(R_AX_ACH1_PAGE_CTRL, val32); in hfc_ch_ctrl()
1150 val32 = SET_WORD(cfg[MAC_AX_DMA_ACH2].min, B_AX_ACH2_MIN_PG) | in hfc_ch_ctrl()
1155 MAC_REG_W32(R_AX_ACH2_PAGE_CTRL_V1, val32); in hfc_ch_ctrl()
1157 MAC_REG_W32(R_AX_ACH2_PAGE_CTRL, val32); in hfc_ch_ctrl()
[all …]
H A Ddbgpkg.c1639 u32 base_addr, strt_pg, residue, i, cnt, val32; in __dump_mac_mem() local
1681 val32 = le32_to_cpu(MAC_REG_R32(i)); in __dump_mac_mem()
1683 *(u32 *)(buf + cnt) = val32; in __dump_mac_mem()
1688 val32); in __dump_mac_mem()
1810 u32 i, j, k, page, val32; in __dump_reg_range() local
1818 val32 = MAC_REG_R32(j + 4 * k); in __dump_reg_range()
1819 PLTFM_MSG_ALWAYS("%08x ", val32); in __dump_reg_range()
1928 u32 val32; in dbg_port_sel() local
1960 val32 = MAC_REG_R32(R_AX_SCH_DBG_SEL); in dbg_port_sel()
1961 val32 |= B_AX_SCH_DBG_EN; in dbg_port_sel()
[all …]
H A Dmport.c344 u32 val32; in _get_port_cfg() local
375 val32 = MAC_REG_R32(cfg_regl[band][port]); in _get_port_cfg()
378 para->val = GET_FIELD(val32, B_AX_NET_TYPE_P0); in _get_port_cfg()
381 para->val = GET_FIELD(val32, B_AX_NET_TYPE_P1); in _get_port_cfg()
384 para->val = GET_FIELD(val32, B_AX_NET_TYPE_P2); in _get_port_cfg()
387 para->val = GET_FIELD(val32, B_AX_NET_TYPE_P3); in _get_port_cfg()
390 para->val = GET_FIELD(val32, B_AX_NET_TYPE_P4); in _get_port_cfg()
396 val32 = MAC_REG_R32(cfg_regl[band][port]); in _get_port_cfg()
397 if (val32 & b_en_l[port]) in _get_port_cfg()
404 val32 = MAC_REG_R32(bcnspc_regl[band][port]); in _get_port_cfg()
[all …]
H A Dla_mode.c21 u32 val32; in mac_lamode_cfg() local
23 val32 = MAC_REG_R32(R_AX_DMAC_FUNC_EN); in mac_lamode_cfg()
24 val32 |= B_AX_BBRPT_EN; in mac_lamode_cfg()
25 MAC_REG_W32(R_AX_DMAC_FUNC_EN, val32); in mac_lamode_cfg()
27 val32 = MAC_REG_R32(R_AX_DMAC_CLK_EN); in mac_lamode_cfg()
28 val32 |= B_AX_BBRPT_CLK_EN; in mac_lamode_cfg()
29 MAC_REG_W32(R_AX_DMAC_CLK_EN, val32); in mac_lamode_cfg()
31 val32 = MAC_REG_R32(R_AX_LA_CFG); in mac_lamode_cfg()
32 val32 &= ~BITS_AX_LA_CFG; in mac_lamode_cfg()
33 val32 |= ((cfg->la_func_en ? B_AX_LA_FEN : 0) | in mac_lamode_cfg()
[all …]
H A Dpwr.c35 u32 val32; in clr_aon_int() local
40 val32 = MAC_REG_R32(R_AX_FWS0IMR); in clr_aon_int()
41 val32 &= ~B_AX_FS_GPIOA_INT_EN; in clr_aon_int()
42 MAC_REG_W32(R_AX_FWS0IMR, val32); in clr_aon_int()
44 val32 = MAC_REG_R32(R_AX_FWS0ISR); in clr_aon_int()
45 val32 |= B_AX_FS_GPIOA_INT; in clr_aon_int()
46 MAC_REG_W32(R_AX_FWS0ISR, val32); in clr_aon_int()
53 u32 val32, cnt, ret = MACSUCCESS; in _patch_aon_int_leave_lps() local
60 val32 = MAC_REG_R32(R_AX_FWS0IMR); in _patch_aon_int_leave_lps()
61 val32 |= B_AX_FS_GPIOA_INT_EN; in _patch_aon_int_leave_lps()
[all …]
/OK3568_Linux_fs/kernel/drivers/edac/
H A Damd8131_edac.c27 static void edac_pci_read_dword(struct pci_dev *dev, int reg, u32 *val32) in edac_pci_read_dword() argument
31 ret = pci_read_config_dword(dev, reg, val32); in edac_pci_read_dword()
37 static void edac_pci_write_dword(struct pci_dev *dev, int reg, u32 val32) in edac_pci_write_dword() argument
41 ret = pci_write_config_dword(dev, reg, val32); in edac_pci_write_dword()
74 u32 val32; in amd8131_pcix_init() local
78 edac_pci_read_dword(dev, REG_MEM_LIM, &val32); in amd8131_pcix_init()
79 if (val32 & MEM_LIMIT_MASK) in amd8131_pcix_init()
80 edac_pci_write_dword(dev, REG_MEM_LIM, val32); in amd8131_pcix_init()
83 edac_pci_read_dword(dev, REG_INT_CTLR, &val32); in amd8131_pcix_init()
84 if (val32 & INT_CTLR_DTS) in amd8131_pcix_init()
[all …]
H A Damd8111_edac.c37 static int edac_pci_read_dword(struct pci_dev *dev, int reg, u32 *val32) in edac_pci_read_dword() argument
41 ret = pci_read_config_dword(dev, reg, val32); in edac_pci_read_dword()
59 static void edac_pci_write_dword(struct pci_dev *dev, int reg, u32 val32) in edac_pci_write_dword() argument
63 ret = pci_write_config_dword(dev, reg, val32); in edac_pci_write_dword()
87 u32 val32; in amd8111_pci_bridge_init() local
93 edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32); in amd8111_pci_bridge_init()
94 if (val32 & PCI_STSCMD_CLEAR_MASK) in amd8111_pci_bridge_init()
95 edac_pci_write_dword(dev, REG_PCI_STSCMD, val32); in amd8111_pci_bridge_init()
98 edac_pci_read_dword(dev, REG_HT_LINK, &val32); in amd8111_pci_bridge_init()
99 if (val32 & HT_LINK_CLEAR_MASK) in amd8111_pci_bridge_init()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/mac/mac_ax/mac_8852b/
H A Dpwr_seq_func_8852b.c29 u32 val32; in mac_pwr_on_sdio_8852b() local
36 val32 = MAC_REG_R32(R_AX_SDIO_BUS_CTRL); in mac_pwr_on_sdio_8852b()
37 MAC_REG_W32(R_AX_SDIO_BUS_CTRL, val32 & ~B_AX_HCI_SUS_REQ); in mac_pwr_on_sdio_8852b()
46 val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); in mac_pwr_on_sdio_8852b()
47 MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~(B_AX_AFSM_WLSUS_EN | in mac_pwr_on_sdio_8852b()
51 val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); in mac_pwr_on_sdio_8852b()
52 MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_DIS_WLBT_PDNSUSEN_SOPC); in mac_pwr_on_sdio_8852b()
55 val32 = MAC_REG_R32(R_AX_WLLPS_CTRL); in mac_pwr_on_sdio_8852b()
56 MAC_REG_W32(R_AX_WLLPS_CTRL, val32 | B_AX_DIS_WLBT_LPSEN_LOPC); in mac_pwr_on_sdio_8852b()
59 val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); in mac_pwr_on_sdio_8852b()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/mac/mac_ax/mac_8852b/
H A Dpwr_seq_func_8852b.c29 u32 val32; in mac_pwr_on_sdio_8852b() local
36 val32 = MAC_REG_R32(R_AX_SDIO_BUS_CTRL); in mac_pwr_on_sdio_8852b()
37 MAC_REG_W32(R_AX_SDIO_BUS_CTRL, val32 & ~B_AX_HCI_SUS_REQ); in mac_pwr_on_sdio_8852b()
46 val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); in mac_pwr_on_sdio_8852b()
47 MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 & ~(B_AX_AFSM_WLSUS_EN | in mac_pwr_on_sdio_8852b()
51 val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); in mac_pwr_on_sdio_8852b()
52 MAC_REG_W32(R_AX_SYS_PW_CTRL, val32 | B_AX_DIS_WLBT_PDNSUSEN_SOPC); in mac_pwr_on_sdio_8852b()
55 val32 = MAC_REG_R32(R_AX_WLLPS_CTRL); in mac_pwr_on_sdio_8852b()
56 MAC_REG_W32(R_AX_WLLPS_CTRL, val32 | B_AX_DIS_WLBT_LPSEN_LOPC); in mac_pwr_on_sdio_8852b()
59 val32 = MAC_REG_R32(R_AX_SYS_PW_CTRL); in mac_pwr_on_sdio_8852b()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtl8xxxu/
H A Drtl8xxxu_8723b.c360 u32 val32, ofdm, mcs; in rtl8723b_set_tx_power() local
368 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); in rtl8723b_set_tx_power()
369 val32 &= 0xffff00ff; in rtl8723b_set_tx_power()
370 val32 |= (cck << 8); in rtl8723b_set_tx_power()
371 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8723b_set_tx_power()
373 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8723b_set_tx_power()
374 val32 &= 0xff; in rtl8723b_set_tx_power()
375 val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); in rtl8723b_set_tx_power()
376 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8723b_set_tx_power()
523 u32 val32; in rtl8723bu_phy_init_antenna_selection() local
[all …]
H A Drtl8xxxu_core.c698 addr, 0, &priv->usb_buf.val32, sizeof(u32), in rtl8xxxu_read32()
700 data = le32_to_cpu(priv->usb_buf.val32); in rtl8xxxu_read32()
754 priv->usb_buf.val32 = cpu_to_le32(val); in rtl8xxxu_write32()
757 addr, 0, &priv->usb_buf.val32, sizeof(u32), in rtl8xxxu_write32()
810 u32 hssia, val32, retval; in rtl8xxxu_read_rfreg() local
814 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2); in rtl8xxxu_read_rfreg()
816 val32 = hssia; in rtl8xxxu_read_rfreg()
818 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK; in rtl8xxxu_read_rfreg()
819 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT); in rtl8xxxu_read_rfreg()
820 val32 |= FPGA0_HSSI_PARM2_EDGE_READ; in rtl8xxxu_read_rfreg()
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H A Drtl8xxxu_8192e.c484 u32 val32, ofdm, mcs; in rtl8192e_set_tx_power() local
493 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); in rtl8192e_set_tx_power()
494 val32 &= 0xffff00ff; in rtl8192e_set_tx_power()
495 val32 |= (cck << 8); in rtl8192e_set_tx_power()
496 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8192e_set_tx_power()
498 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8192e_set_tx_power()
499 val32 &= 0xff; in rtl8192e_set_tx_power()
500 val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); in rtl8192e_set_tx_power()
501 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8192e_set_tx_power()
525 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); in rtl8192e_set_tx_power()
[all …]

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