Home
last modified time | relevance | path

Searched refs:uart0_parents (Results 1 – 5 of 5) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/clk/spear/
H A Dspear3xx_clock.c130 static const char *uart0_parents[] = { "pll3_clk", "uart_syn_gclk", }; variable
442 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, in spear3xx_clk_init()
443 ARRAY_SIZE(uart0_parents), in spear3xx_clk_init()
H A Dspear1340_clock.c421 static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk", variable
638 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, in spear1340_clk_init()
639 ARRAY_SIZE(uart0_parents), in spear1340_clk_init()
H A Dspear1310_clock.c360 static const char *uart0_parents[] = { "pll5_clk", "uart_syn_gclk", }; variable
559 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, in spear1310_clk_init()
560 ARRAY_SIZE(uart0_parents), in spear1310_clk_init()
/OK3568_Linux_fs/kernel/drivers/clk/mediatek/
H A Dclk-mt8516.c73 static const char * const uart0_parents[] __initconst = { variable
363 MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
H A Dclk-mt8167.c87 static const char * const uart0_parents[] __initconst = { variable
523 MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,